Intel® Integrated Performance Primitives (Intel® IPP) is a software library that provides a broad range of functionality, including general signal and image processing, computer vision, data compression, cryptography, and string manipulation.

Intel IPP is installed as part of the following suites:

The library is also provided as a standalone package under the Community Licensing Program.

The majority of Intel IPP functions offered in different product suites are the same. But there are several Intel IPP libraries or domains that are only included in some product packages. The following table provides a summary of Intel IPP functionality for different product suites:

Intel IPP Functionality Intel® Parallel Studio XE Intel® System Studio Intel® IPP Standalone
Common function domains (string operations, cryptography, computer vision, data compression, image processing, signal processing, etc.) Yes Yes Yes
Long Term Evolution functions for the embedded domain No Yes No
Intel® IPP libraries for Android* and Intel® Quark™ platforms No Yes Yes
Intel® IPP libraries for Intel® Xeon Phi™ Coprocessor Yes No Yes


Set Environment Variables

After installing Intel IPP, set the IPPROOT, LD_LIBRARY_PATH, and NLSPATH environment variables by running the script appropriate to your target platform architecture. The scripts are available in <install dir>/ipp/bin.

By default, the <install dir> is:

  • For root users: /opt/intel/
  • For non-root users: $HOME/intel/

System Requirements

Build and Run Your First Intel® IPP Application

The code example below represents a short application to help you get started with Intel IPP:

#include "ipp.h"
#include <stdio.h>
int main(int argc, char* argv[])
   const IppLibraryVersion *lib;
   IppStatus status;
   Ipp64u mask, emask;

   /* Init IPP library */
   /* Get IPP library version info */
   lib = ippGetLibVersion();
   printf("%s %s\n", lib->Name, lib->Version);

   /* Get CPU features and features enabled with selected library level */
   status = ippGetCpuFeatures( &mask, 0 );
   if( ippStsNoErr == status ) {
      emask = ippGetEnabledCpuFeatures();
      printf("Features supported by CPU\tby IPP\n");
      printf("  ippCPUID_MMX        = ");
      printf("%c\t%c\t",( mask & ippCPUID_MMX ) ? 'Y':'N',( emask & ippCPUID_MMX ) ? 'Y':'N');
      printf("Intel(R) Architecture MMX technology supported\n");
      printf("  ippCPUID_SSE        = ");
      printf("%c\t%c\t",( mask & ippCPUID_SSE ) ? 'Y':'N',( emask & ippCPUID_SSE ) ? 'Y':'N');
      printf("Intel(R) Streaming SIMD Extensions\n");
      printf("  ippCPUID_SSE2       = ");
      printf("%c\t%c\t",( mask & ippCPUID_SSE2 ) ? 'Y':'N',( emask & ippCPUID_SSE2 ) ? 'Y':'N');
      printf("Intel(R) Streaming SIMD Extensions 2\n");
      printf("  ippCPUID_SSE3       = ");
      printf("%c\t%c\t",( mask & ippCPUID_SSE3 ) ? 'Y':'N',( emask & ippCPUID_SSE3 ) ? 'Y':'N');
      printf("Intel(R) Streaming SIMD Extensions 3\n");
      printf("  ippCPUID_SSSE3      = ");
      printf("%c\t%c\t",( mask & ippCPUID_SSSE3 ) ? 'Y':'N',( emask & ippCPUID_SSSE3 ) ? 'Y':'N');
      printf("Intel(R) Supplemental Streaming SIMD Extensions 3\n");
      printf("  ippCPUID_MOVBE      = ");
      printf("%c\t%c\t",( mask & ippCPUID_MOVBE ) ? 'Y':'N',( emask & ippCPUID_MOVBE ) ? 'Y':'N');
      printf("The processor supports MOVBE instruction\n");
      printf("  ippCPUID_SSE41      = ");
      printf("%c\t%c\t",( mask & ippCPUID_SSE41 ) ? 'Y':'N',( emask & ippCPUID_SSE41 ) ? 'Y':'N');
      printf("Intel(R) Streaming SIMD Extensions 4.1\n");
      printf("  ippCPUID_SSE42      = ");
      printf("%c\t%c\t",( mask & ippCPUID_SSE42 ) ? 'Y':'N',( emask & ippCPUID_SSE42 ) ? 'Y':'N');
      printf("Intel(R) Streaming SIMD Extensions 4.2\n");
      printf("  ippCPUID_AVX        = ");
      printf("%c\t%c\t",( mask & ippCPUID_AVX ) ? 'Y':'N',( emask & ippCPUID_AVX ) ? 'Y':'N');
      printf("Intel(R) Advanced Vector Extensions instruction set\n");
      printf("  ippAVX_ENABLEDBYOS  = ");
      printf("%c\t%c\t",( mask & ippAVX_ENABLEDBYOS ) ? 'Y':'N',( emask & ippAVX_ENABLEDBYOS ) ? 'Y':'N');
      printf("The operating system supports Intel(R) AVX\n");
      printf("  ippCPUID_AES        = ");
      printf("%c\t%c\t",( mask & ippCPUID_AES ) ? 'Y':'N',( emask & ippCPUID_AES ) ? 'Y':'N');
      printf("Intel(R) AES instruction\n");
      printf("  ippCPUID_SHA        = ");
      printf("%c\t%c\t",( mask & ippCPUID_SHA ) ? 'Y':'N',( emask & ippCPUID_SHA ) ? 'Y':'N');
      printf("Intel(R) SHA new instructions\n");
      printf("  ippCPUID_CLMUL      = ");
      printf("%c\t%c\t",( mask & ippCPUID_CLMUL ) ? 'Y':'N',( emask & ippCPUID_CLMUL ) ? 'Y':'N');
      printf("PCLMULQDQ instruction\n");
      printf("  ippCPUID_RDRAND     = ");
      printf("%c\t%c\t",( mask & ippCPUID_RDRAND ) ? 'Y':'N',( emask & ippCPUID_RDRAND ) ? 'Y':'N');
      printf("Read Random Number instructions\n");
      printf("  ippCPUID_F16C       = ");
      printf("%c\t%c\t",( mask & ippCPUID_F16C ) ? 'Y':'N',( emask & ippCPUID_F16C ) ? 'Y':'N');
      printf("Float16 instructions\n");
      printf("  ippCPUID_AVX2       = ");
      printf("%c\t%c\t",( mask & ippCPUID_AVX2 ) ? 'Y':'N',( emask & ippCPUID_AVX2 ) ? 'Y':'N');
      printf("Intel(R) Advanced Vector Extensions 2 instruction set\n");
      printf("  ippCPUID_AVX512F    = ");
      printf("%c\t%c\t",( mask & ippCPUID_AVX512F ) ? 'Y':'N',( emask & ippCPUID_AVX512F ) ? 'Y':'N');
      printf("Intel(R) Advanced Vector Extensions 3.1 instruction set\n");
      printf("  ippCPUID_AVX512CD   = ");
      printf("%c\t%c\t",( mask & ippCPUID_AVX512CD ) ? 'Y':'N',( emask & ippCPUID_AVX512CD ) ? 'Y':'N');
      printf("Intel(R) Advanced Vector Extensions CD (Conflict Detection) instruction set\n");
      printf("  ippCPUID_AVX512ER   = ");
      printf("%c\t%c\t",( mask & ippCPUID_AVX512ER ) ? 'Y':'N',( emask & ippCPUID_AVX512ER ) ? 'Y':'N');
      printf("Intel(R) Advanced Vector Extensions ER instruction set\n");
      printf("  ippCPUID_ADCOX      = ");
      printf("%c\t%c\t",( mask & ippCPUID_ADCOX ) ? 'Y':'N',( emask & ippCPUID_ADCOX ) ? 'Y':'N');
      printf("ADCX and ADOX instructions\n");
      printf("  ippCPUID_RDSEED     = ");
      printf("%c\t%c\t",( mask & ippCPUID_RDSEED ) ? 'Y':'N',( emask & ippCPUID_RDSEED ) ? 'Y':'N');
      printf("The RDSEED instruction\n");
      printf("  ippCPUID_PREFETCHW  = ");
      printf("%c\t%c\t",( mask & ippCPUID_PREFETCHW ) ? 'Y':'N',( emask & ippCPUID_PREFETCHW ) ? 'Y':'N');
      printf("The PREFETCHW instruction\n");
      printf("  ippCPUID_KNC        = ");
      printf("%c\t%c\t",( mask & ippCPUID_KNC ) ? 'Y':'N',( emask & ippCPUID_KNC ) ? 'Y':'N');
      printf("Intel® Xeon Phi™ Coprocessor instruction set\n");
   return 0;

This application consists of three sections:

  1. Initialize the Intel IPP library. This stage is required to take advantage of full Intel IPP optimization. With ippInit(), the best implementation layer is dispatched at runtime; otherwise, the least optimized implementation is chosen. If the Intel IPP application runs without ippInit(), the Intel IPP library is auto-initialized with the first call of the Intel IPP function from any domain that is different from ippCore. In certain debugging scenarios, it is helpful to force a specific implementation layer using ippSetCpuFeatures(), instead of the best as chosen by the dispatcher.
  2. Get the library layer name and version. You can also get the version information using the ippversion.h file located in the /include directory.
  3. Show the hardware optimizations used by the selected library layer and supported by CPU.

To build the code example above, follow the steps:

  1. Paste the code into the editor of your choice.
  2. Make sure the compiler and Intel IPP variables are set in your shell. For information on how to set environment variables see Prerequisites.
  3. Compile with the following command: icc ipptest.cpp -o ipptest -I $IPPROOT/include -L $IPPROOT/lib/<arch> -lippi -lipps -lippcore. For more information about which Intel IPP libraries you need to link to, see Intel IPP Developer Guide. For offload compilation on Intel® Xeon Ph™ Coprocessors, use the following command: icc - qoption,link,"--no-undefined" $< -o application test.o -qoffload-option,mic,link," -L$(IPPROOT)/lib/mic -lippi -lipps -lippcore". For more information on how to use Intel IPP on Intel® Xeon Phi™ Coprocessors, refer to the Multi-threading Example for Intel® Xeon Phi™ Coprocessor (ipp_thread_mic) and respective documentation (ipp-examples.html) available in the components_and_examples_<target>.zip archive at the <install_dir>/ipp/components subdirectory.
  4. Run the application.

Training and Documentation



Online Training

Intel® IPP training resources.

Intel® IPP Developer Reference

Contains detailed descriptions of the Intel IPP functions and interfaces for signal, image processing, and computer vision.

Intel® IPP Cryptography Developer Reference


Contains detailed descriptions of the Intel IPP cryptography functions. This document is installed with the Intel IPP Crypto Add-on to the ippcp folder inside the Intel IPP documentation directory.

Intel® IPP Developer Guide

Provides detailed guidance on Intel IPP library configuration, development environment, and linkage modes.

Image Blurring and Rotation with Intel® IPP Tutorial and Sample

Demonstrates how to implement box blurring of an image using Intel IPP image processing functions. The tutorial and sample bundle is available for download from Intel® Software Product Samples and Tutorials.

Intel® IPP Examples

Include a collection of example programs that demonstrate the various features of the Intel IPP library. These programs are located in the components_and_examples_<target>.zip archive at the <install_dir>/ipp/components subdirectory. The archive also includes the ipp-examples.html documentation file at the documentation subdirectory.

Intel® Integrated Performance Primitives

Intel® IPP product page. See this page for support and online documentation.

Legal Information

Intel, and the Intel logo are trademarks of Intel Corporation in the U.S. and/or other countries.

*Other names and brands may be claimed as the property of others.

© Intel Corporation

Optimization Notice

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804