This section provides reference for hardware events that can be monitored for the CPU(s):
- Intel® Xeon® E5/E7 v3 processor
The following performance-monitoring events are supported:
ARITH.DIVIDER_UOPS
Any uop executed by the Divider. (This includes all divide uops, sqrt, ...)
AVX_INSTS.ALL
Note that a whole rep string only counts AVX_INST.ALL once.
BACLEARS.ANY
Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.
BR_INST_EXEC.ALL_BRANCHES
Speculative and retired branches
BR_INST_EXEC.ALL_CONDITIONAL
Speculative and retired macro-conditional branches
BR_INST_EXEC.ALL_DIRECT_JMP
Speculative and retired macro-unconditional branches excluding calls and indirects
BR_INST_EXEC.ALL_DIRECT_NEAR_CALL
Speculative and retired direct near calls
BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET
Speculative and retired indirect branches excluding calls and returns
BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN
Speculative and retired indirect return branches.
BR_INST_EXEC.NONTAKEN_CONDITIONAL
Not taken macro-conditional branches
BR_INST_EXEC.TAKEN_CONDITIONAL
Taken speculative and retired macro-conditional branches
BR_INST_EXEC.TAKEN_DIRECT_JUMP
Taken speculative and retired macro-conditional branch instructions excluding calls and indirects
BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL
Taken speculative and retired direct near calls
BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET
Taken speculative and retired indirect branches excluding calls and returns
BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL
Taken speculative and retired indirect calls
BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN
Taken speculative and retired indirect branches with return mnemonic
BR_INST_RETIRED.ALL_BRANCHES
All (macro) branch instructions retired.
BR_INST_RETIRED.ALL_BRANCHES_PS
All (macro) branch instructions retired.
BR_INST_RETIRED.CONDITIONAL
Conditional branch instructions retired.
BR_INST_RETIRED.CONDITIONAL_PS
Conditional branch instructions retired.
BR_INST_RETIRED.FAR_BRANCH
Far branch instructions retired.
BR_INST_RETIRED.NEAR_CALL
Direct and indirect near call instructions retired.
BR_INST_RETIRED.NEAR_CALL_PS
Direct and indirect near call instructions retired.
BR_INST_RETIRED.NEAR_CALL_R3
Direct and indirect macro near call instructions retired (captured in ring 3).
BR_INST_RETIRED.NEAR_CALL_R3_PS
Direct and indirect macro near call instructions retired (captured in ring 3).
BR_INST_RETIRED.NEAR_RETURN
Return instructions retired.
BR_INST_RETIRED.NEAR_RETURN_PS
Return instructions retired.
BR_INST_RETIRED.NEAR_TAKEN
Taken branch instructions retired.
BR_INST_RETIRED.NEAR_TAKEN_PS
Taken branch instructions retired.
BR_INST_RETIRED.NOT_TAKEN
Not taken branch instructions retired.
BR_MISP_EXEC.ALL_BRANCHES
Speculative and retired mispredicted macro conditional branches
BR_MISP_EXEC.ALL_CONDITIONAL
Speculative and retired mispredicted macro conditional branches
BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET
Mispredicted indirect branches excluding calls and returns
BR_MISP_EXEC.NONTAKEN_CONDITIONAL
Not taken speculative and retired mispredicted macro conditional branches
BR_MISP_EXEC.TAKEN_CONDITIONAL
Taken speculative and retired mispredicted macro conditional branches
BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET
Taken speculative and retired mispredicted indirect branches excluding calls and returns
BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL
Taken speculative and retired mispredicted indirect calls
BR_MISP_EXEC.TAKEN_RETURN_NEAR
Taken speculative and retired mispredicted indirect branches with return mnemonic
BR_MISP_RETIRED.ALL_BRANCHES
All mispredicted macro branch instructions retired.
BR_MISP_RETIRED.ALL_BRANCHES_PS
This event counts all mispredicted branch instructions retired. This is a precise event.
BR_MISP_RETIRED.CONDITIONAL
Mispredicted conditional branch instructions retired.
BR_MISP_RETIRED.CONDITIONAL_PS
Mispredicted conditional branch instructions retired.
BR_MISP_RETIRED.NEAR_TAKEN
number of near branch instructions retired that were mispredicted and taken.
BR_MISP_RETIRED.NEAR_TAKEN_PS
number of near branch instructions retired that were mispredicted and taken.
CPL_CYCLES.RING0
Unhalted core cycles when the thread is in ring 0
CPL_CYCLES.RING0_TRANS
Number of intervals between processor halts while thread is in ring 0
CPL_CYCLES.RING123
Unhalted core cycles when thread is in rings 1, 2, or 3
CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE
Count XClk pulses when this thread is unhalted and the other thread is halted.
CPU_CLK_THREAD_UNHALTED.REF_XCLK
Reference cycles when the thread is unhalted (counts at 100 MHz rate)
CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY
Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate)
CPU_CLK_UNHALTED.REF_TSC
This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state.
CPU_CLK_UNHALTED.THREAD
This event counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling.
CPU_CLK_UNHALTED.THREAD_ANY
Core cycles when at least one thread on the physical core is not in halt state
CPU_CLK_UNHALTED.THREAD_P
Thread cycles when thread is not in halt state
CPU_CLK_UNHALTED.THREAD_P_ANY
Core cycles when at least one thread on the physical core is not in halt state
CYCLE_ACTIVITY.CYCLES_L1D_PENDING
Cycles with pending L1 cache miss loads.
CYCLE_ACTIVITY.CYCLES_L2_PENDING
Cycles with pending L2 cache miss loads.
CYCLE_ACTIVITY.CYCLES_LDM_PENDING
Cycles with pending memory loads.
CYCLE_ACTIVITY.CYCLES_NO_EXECUTE
This event counts cycles during which no instructions were executed in the execution stage of the pipeline.
CYCLE_ACTIVITY.STALLS_L1D_PENDING
Execution stalls due to L1 data cache misses
CYCLE_ACTIVITY.STALLS_L2_PENDING
Execution stalls due to L2 cache misses.
CYCLE_ACTIVITY.STALLS_LDM_PENDING
This event counts cycles during which no instructions were executed in the execution stage of the pipeline and there were memory instructions pending (waiting for data).
DSB2MITE_SWITCHES.PENALTY_CYCLES
Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.
DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK
Load misses in all DTLB levels that cause page walks
DTLB_LOAD_MISSES.PDE_CACHE_MISS
DTLB demand load misses with low part of linear-to-physical address translation missed
DTLB_LOAD_MISSES.STLB_HIT
Load operations that miss the first DTLB level but hit the second and do not cause page walks
DTLB_LOAD_MISSES.STLB_HIT_2M
This event counts load operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.
DTLB_LOAD_MISSES.STLB_HIT_4K
This event counts load operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.
DTLB_LOAD_MISSES.WALK_COMPLETED
Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.
DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M
Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).
DTLB_LOAD_MISSES.WALK_COMPLETED_4K
Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).
DTLB_LOAD_MISSES.WALK_DURATION
This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses.
DTLB_STORE_MISSES.MISS_CAUSES_A_WALK
Store misses in all DTLB levels that cause page walks
DTLB_STORE_MISSES.PDE_CACHE_MISS
DTLB store misses with low part of linear-to-physical address translation missed
DTLB_STORE_MISSES.STLB_HIT
Store operations that miss the first TLB level but hit the second and do not cause page walks
DTLB_STORE_MISSES.STLB_HIT_2M
This event counts store operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.
DTLB_STORE_MISSES.STLB_HIT_4K
This event counts store operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.
DTLB_STORE_MISSES.WALK_COMPLETED
Store misses in all DTLB levels that cause completed page walks
DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M
Store misses in all DTLB levels that cause completed page walks (2M/4M)
DTLB_STORE_MISSES.WALK_COMPLETED_4K
Store miss in all TLB levels causes a page walk that completes. (4K)
DTLB_STORE_MISSES.WALK_DURATION
This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB store misses.
EPT.WALK_CYCLES
Cycle count for an Extended Page table walk.
FP_ASSIST.ANY
Cycles with any input/output SSE or FP assist
FP_ASSIST.SIMD_OUTPUT
Number of SIMD FP assists due to Output values
FP_ASSIST.X87_OUTPUT
Number of X87 assists due to output value.
HLE_RETIRED.ABORTED
Number of times an HLE execution aborted due to any reasons (multiple categories may count as one).
HLE_RETIRED.ABORTED_MISC1
Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).
HLE_RETIRED.ABORTED_MISC2
Number of times an HLE execution aborted due to uncommon conditions
HLE_RETIRED.ABORTED_MISC3
Number of times an HLE execution aborted due to HLE-unfriendly instructions
HLE_RETIRED.ABORTED_MISC4
Number of times an HLE execution aborted due to incompatible memory type
HLE_RETIRED.ABORTED_MISC5
Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)
HLE_RETIRED.ABORTED_PS
Number of times an HLE execution aborted due to any reasons (multiple categories may count as one).
HLE_RETIRED.COMMIT
Number of times an HLE execution successfully committed
HLE_RETIRED.START
Number of times an HLE execution started.
ICACHE.HIT
Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches
ICACHE.IFDATA_STALL
Cycles where a code fetch is stalled due to L1 instruction-cache miss.
ICACHE.IFETCH_STALL
Cycles where a code fetch is stalled due to L1 instruction-cache miss.
ICACHE.MISSES
This event counts Instruction Cache (ICACHE) misses.
IDQ.ALL_DSB_CYCLES_4_UOPS
Cycles Decode Stream Buffer (DSB) is delivering 4 Uops
IDQ.ALL_DSB_CYCLES_ANY_UOPS
Cycles Decode Stream Buffer (DSB) is delivering any Uop
IDQ.ALL_MITE_CYCLES_4_UOPS
Cycles MITE is delivering 4 Uops
IDQ.ALL_MITE_CYCLES_ANY_UOPS
Cycles MITE is delivering any Uop
IDQ.DSB_CYCLES
Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path
IDQ.DSB_UOPS
Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path
IDQ.EMPTY
Instruction Decode Queue (IDQ) empty cycles
IDQ.MITE_ALL_UOPS
Uops delivered to Instruction Decode Queue (IDQ) from MITE path
IDQ.MITE_CYCLES
Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path
IDQ.MITE_UOPS
Uops delivered to Instruction Decode Queue (IDQ) from MITE path
IDQ.MS_CYCLES
This event counts cycles during which the microcode sequencer assisted the Front-end in delivering uops. Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder. Using other instructions, if possible, will usually improve performance.
IDQ.MS_DSB_CYCLES
Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy
IDQ.MS_DSB_OCCUR
Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy
IDQ.MS_DSB_UOPS
Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy
IDQ.MS_MITE_UOPS
Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy
IDQ.MS_SWITCHES
Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer
IDQ.MS_UOPS
This event counts uops delivered by the Front-end with the assistance of the microcode sequencer. Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder. Using other instructions, if possible, will usually improve performance.
IDQ_UOPS_NOT_DELIVERED.CORE
This event count the number of undelivered (unallocated) uops from the Front-end to the Resource Allocation Table (RAT) while the Back-end of the processor is not stalled. The Front-end can allocate up to 4 uops per cycle so this event can increment 0-4 times per cycle depending on the number of unallocated uops. This event is counted on a per-core basis.
IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE
This event counts the number cycles during which the Front-end allocated exactly zero uops to the Resource Allocation Table (RAT) while the Back-end of the processor is not stalled. This event is counted on a per-core basis.
IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK
Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.
IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE
Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled
IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE
Cycles with less than 2 uops delivered by the front end.
IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE
Cycles with less than 3 uops delivered by the front end.
ILD_STALL.IQ_FULL
Stall cycles because IQ is full
ILD_STALL.LCP
This event counts cycles where the decoder is stalled on an instruction with a length changing prefix (LCP).
INST_RETIRED.ANY
This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. INST_RETIRED.ANY is counted by a designated fixed counter, leaving the programmable counters available for other events. Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.
INST_RETIRED.ANY_P
Number of instructions retired. General Counter - architectural event
INST_RETIRED.PREC_DIST
Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution
INT_MISC.RECOVERY_CYCLES
This event counts the number of cycles spent waiting for a recovery after an event such as a processor nuke, JEClear, assist, hle/rtm abort etc....
INT_MISC.RECOVERY_CYCLES_ANY
Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke)
ITLB.ITLB_FLUSH
Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.
ITLB_MISSES.MISS_CAUSES_A_WALK
Misses at all ITLB levels that cause page walks
ITLB_MISSES.STLB_HIT
Operations that miss the first ITLB level but hit the second and do not cause any page walks
ITLB_MISSES.STLB_HIT_2M
Code misses that miss the DTLB and hit the STLB (2M)
ITLB_MISSES.STLB_HIT_4K
Core misses that miss the DTLB and hit the STLB (4K)
ITLB_MISSES.WALK_COMPLETED
Misses in all ITLB levels that cause completed page walks
ITLB_MISSES.WALK_COMPLETED_2M_4M
Code miss in all TLB levels causes a page walk that completes. (2M/4M)
ITLB_MISSES.WALK_COMPLETED_4K
Code miss in all TLB levels causes a page walk that completes. (4K)
ITLB_MISSES.WALK_DURATION
This event counts cycles when the page miss handler (PMH) is servicing page walks caused by ITLB misses.
L1D.REPLACEMENT
This event counts when new data lines are brought into the L1 Data cache, which cause other lines to be evicted from the cache.
L1D_PEND_MISS.FB_FULL
Cycles a demand request was blocked due to Fill Buffers inavailability
L1D_PEND_MISS.PENDING
L1D miss oustandings duration in cycles
L1D_PEND_MISS.PENDING_CYCLES
Cycles with L1D load Misses outstanding.
L1D_PEND_MISS.PENDING_CYCLES_ANY
Cycles with L1D load Misses outstanding from any thread on physical core
L1D_PEND_MISS.REQUEST_FB_FULL
Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch. HWP are e
L2_DEMAND_RQSTS.WB_HIT
Not rejected writebacks that hit L2 cache
L2_LINES_IN.ALL
This event counts the number of L2 cache lines brought into the L2 cache. Lines are filled into the L2 cache when there was an L2 miss.
L2_LINES_IN.E
L2 cache lines in E state filling L2
L2_LINES_IN.I
L2 cache lines in I state filling L2
L2_LINES_IN.S
L2 cache lines in S state filling L2
L2_LINES_OUT.DEMAND_CLEAN
Clean L2 cache lines evicted by demand
L2_LINES_OUT.DEMAND_DIRTY
Dirty L2 cache lines evicted by demand
L2_RQSTS.ALL_CODE_RD
L2 code requests
L2_RQSTS.ALL_DEMAND_DATA_RD
Demand Data Read requests
L2_RQSTS.ALL_DEMAND_MISS
Demand requests that miss L2 cache
L2_RQSTS.ALL_DEMAND_REFERENCES
Demand requests to L2 cache
L2_RQSTS.ALL_PF
Requests from L2 hardware prefetchers
L2_RQSTS.ALL_RFO
RFO requests to L2 cache
L2_RQSTS.CODE_RD_HIT
L2 cache hits when fetching instructions, code reads.
L2_RQSTS.CODE_RD_MISS
L2 cache misses when fetching instructions
L2_RQSTS.DEMAND_DATA_RD_HIT
Demand Data Read requests that hit L2 cache
L2_RQSTS.DEMAND_DATA_RD_MISS
Demand Data Read miss L2, no rejects
L2_RQSTS.L2_PF_HIT
L2 prefetch requests that hit L2 cache
L2_RQSTS.L2_PF_MISS
L2 prefetch requests that miss L2 cache
L2_RQSTS.MISS
All requests that miss L2 cache
L2_RQSTS.REFERENCES
All L2 requests
L2_RQSTS.RFO_HIT
RFO requests that hit L2 cache
L2_RQSTS.RFO_MISS
RFO requests that miss L2 cache
L2_TRANS.ALL_PF
L2 or L3 HW prefetches that access L2 cache
L2_TRANS.ALL_REQUESTS
Transactions accessing L2 pipe
L2_TRANS.CODE_RD
L2 cache accesses when fetching instructions
L2_TRANS.DEMAND_DATA_RD
Demand Data Read requests that access L2 cache
L2_TRANS.L1D_WB
L1D writebacks that access L2 cache
L2_TRANS.L2_FILL
L2 fill requests that access L2 cache
L2_TRANS.L2_WB
L2 writebacks that access L2 cache
L2_TRANS.RFO
RFO requests that access L2 cache
LD_BLOCKS.NO_SR
The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use
LD_BLOCKS.STORE_FORWARD
This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceding smaller uncompleted store. The penalty for blocked store forwarding is that the load must wait for the store to write its value to the cache before it can be issued.
LD_BLOCKS_PARTIAL.ADDRESS_ALIAS
Aliasing occurs when a load is issued after a store and their memory addresses are offset by 4K. This event counts the number of loads that aliased with a preceding store, resulting in an extended address check in the pipeline which can have a performance impact.
LOAD_HIT_PRE.HW_PF
Not software-prefetch load dispatches that hit FB allocated for hardware prefetch
LOAD_HIT_PRE.SW_PF
Not software-prefetch load dispatches that hit FB allocated for software prefetch
LOCK_CYCLES.CACHE_LOCK_DURATION
Cycles when L1D is locked
LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION
Cycles when L1 and L2 are locked due to UC or split lock
LONGEST_LAT_CACHE.MISS
Core-originated cacheable demand requests missed L3
LONGEST_LAT_CACHE.REFERENCE
Core-originated cacheable demand requests that refer to L3
LSD.CYCLES_4_UOPS
Cycles 4 Uops delivered by the LSD, but didn't come from the decoder
LSD.CYCLES_ACTIVE
Cycles Uops delivered by the LSD, but didn't come from the decoder
LSD.UOPS
Number of Uops delivered by the LSD.
MACHINE_CLEARS.COUNT
Number of machine clears (nukes) of any type.
MACHINE_CLEARS.CYCLES
Cycles there was a Nuke. Account for both thread-specific and All Thread Nukes.
MACHINE_CLEARS.MASKMOV
This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.
MACHINE_CLEARS.MEMORY_ORDERING
This event counts the number of memory ordering machine clears detected. Memory ordering machine clears can result from memory address aliasing or snoops from another hardware thread or core to data inflight in the pipeline. Machine clears can have a significant performance impact if they are happening frequently.
MACHINE_CLEARS.SMC
This event is incremented when self-modifying code (SMC) is detected, which causes a machine clear. Machine clears can have a significant performance impact if they are happening frequently.
MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT
Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache.
MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM
Retired load uops which data sources were HitM responses from shared L3.
MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM_PS
This event counts retired load uops that hit in the L3 cache, but required a cross-core snoop which resulted in a HITM (hit modified) in an on-pkg core cache. This does not include hardware prefetches. This is a precise event.
MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT_PS
This event counts retired load uops that hit in the L3 cache, but required a cross-core snoop which resulted in a HIT in an on-pkg core cache. This does not include hardware prefetches. This is a precise event.
MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS
Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.
MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS_PS
Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.
MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE
Retired load uops which data sources were hits in L3 without snoops required.
MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE_PS
Retired load uops which data sources were hits in L3 without snoops required.
MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM
This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches.
MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM_PS
This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches. This is a precise event.
MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM
Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI)
MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM_PS
Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI) (Precise Event)
MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD
Retired load uop whose Data Source was: forwarded from remote cache
MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD_PS
tbd
MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM
Retired load uop whose Data Source was: Remote cache HITM
MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM_PS
Retired load uop whose Data Source was: Remote cache HITM (Precise Event)
MEM_LOAD_UOPS_RETIRED.HIT_LFB
Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.
MEM_LOAD_UOPS_RETIRED.HIT_LFB_PS
Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.
MEM_LOAD_UOPS_RETIRED.L1_HIT
Retired load uops with L1 cache hits as data sources.
MEM_LOAD_UOPS_RETIRED.L1_HIT_PS
Retired load uops with L1 cache hits as data sources.
MEM_LOAD_UOPS_RETIRED.L1_MISS
Retired load uops misses in L1 cache as data sources.
MEM_LOAD_UOPS_RETIRED.L1_MISS_PS
This event counts retired load uops in which data sources missed in the L1 cache. This does not include hardware prefetches. This is a precise event.
MEM_LOAD_UOPS_RETIRED.L2_HIT
Retired load uops with L2 cache hits as data sources.
MEM_LOAD_UOPS_RETIRED.L2_HIT_PS
Retired load uops with L2 cache hits as data sources.
MEM_LOAD_UOPS_RETIRED.L2_MISS
Miss in mid-level (L2) cache. Excludes Unknown data-source.
MEM_LOAD_UOPS_RETIRED.L2_MISS_PS
Retired load uops with L2 cache misses as data sources.
MEM_LOAD_UOPS_RETIRED.L3_HIT
Retired load uops which data sources were data hits in L3 without snoops required.
MEM_LOAD_UOPS_RETIRED.L3_HIT_PS
This event counts retired load uops in which data sources were data hits in the L3 cache without snoops required. This does not include hardware prefetches. This is a precise event.
MEM_LOAD_UOPS_RETIRED.L3_MISS
Miss in last-level (L3) cache. Excludes Unknown data-source.
MEM_LOAD_UOPS_RETIRED.L3_MISS_PS
Miss in last-level (L3) cache. Excludes Unknown data-source.
MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128
Loads with latency value being above 128
MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16
Loads with latency value being above 16
MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256
Loads with latency value being above 256
MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32
Loads with latency value being above 32
MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4
Loads with latency value being above 4
MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512
Loads with latency value being above 512
MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64
Loads with latency value being above 64
MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8
Loads with latency value being above 8
MEM_UOPS_RETIRED.ALL_LOADS
Load uops retired to architected path with filter on bits 0 and 1 applied.
MEM_UOPS_RETIRED.ALL_LOADS_PS
Load uops retired to architected path with filter on bits 0 and 1 applied.
MEM_UOPS_RETIRED.ALL_STORES
Store uops retired to architected path with filter on bits 0 and 1 applied.
MEM_UOPS_RETIRED.ALL_STORES_PS
This event counts all store uops retired. This is a precise event.
MEM_UOPS_RETIRED.LOCK_LOADS
Load uops with locked access retired to architected path.
MEM_UOPS_RETIRED.LOCK_LOADS_PS
Load uops with locked access retired to architected path.
MEM_UOPS_RETIRED.SPLIT_LOADS
Line-splitted load uops retired to architected path.
MEM_UOPS_RETIRED.SPLIT_LOADS_PS
This event counts load uops retired which had memory addresses spilt across 2 cache lines. A line split is across 64B cache-lines which may include a page split (4K). This is a precise event.
MEM_UOPS_RETIRED.SPLIT_STORES
Line-splitted store uops retired to architected path.
MEM_UOPS_RETIRED.SPLIT_STORES_PS
This event counts store uops retired which had memory addresses spilt across 2 cache lines. A line split is across 64B cache-lines which may include a page split (4K). This is a precise event.
MEM_UOPS_RETIRED.STLB_MISS_LOADS
Load uops with true STLB miss retired to architected path.
MEM_UOPS_RETIRED.STLB_MISS_LOADS_PS
Load uops with true STLB miss retired to architected path.
MEM_UOPS_RETIRED.STLB_MISS_STORES
Store uops with true STLB miss retired to architected path.
MEM_UOPS_RETIRED.STLB_MISS_STORES_PS
Store uops true STLB miss retired to architected path.
MISALIGN_MEM_REF.LOADS
Speculative cache line split load uops dispatched to L1 cache
MISALIGN_MEM_REF.STORES
Speculative cache line split STA uops dispatched to L1 cache
MOVE_ELIMINATION.INT_ELIMINATED
Number of integer Move Elimination candidate uops that were eliminated.
MOVE_ELIMINATION.INT_NOT_ELIMINATED
Number of integer Move Elimination candidate uops that were not eliminated.
MOVE_ELIMINATION.SIMD_ELIMINATED
Number of SIMD Move Elimination candidate uops that were eliminated.
MOVE_ELIMINATION.SIMD_NOT_ELIMINATED
Number of SIMD Move Elimination candidate uops that were not eliminated.
OFFCORE_REQUESTS.ALL_DATA_RD
Demand and prefetch data reads
OFFCORE_REQUESTS.DEMAND_CODE_RD
Cacheable and noncachaeble code read requests
OFFCORE_REQUESTS.DEMAND_DATA_RD
Demand Data Read requests sent to uncore
OFFCORE_REQUESTS.DEMAND_RFO
Demand RFO requests including regular RFOs, locks, ItoM
OFFCORE_REQUESTS_BUFFER.SQ_FULL
Offcore requests buffer cannot take more entries for this thread core.
OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD
Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore
OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD
Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore
OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD
Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore
OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD
Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle
OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD
Offcore outstanding Demand Data Read transactions in uncore queue.
OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6
Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue
OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO
Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore
OFFCORE_RESPONSE
Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction
OFFCORE_RESPONSE:request=ALL_CODE_RD:response=LLC_HIT.ANY_RESPONSE
Counts all demand & prefetch code reads that hit in the L3
OFFCORE_RESPONSE:request=ALL_CODE_RD:response=LLC_HIT.HITM_OTHER_CORE
Counts all demand & prefetch code reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
OFFCORE_RESPONSE:request=ALL_CODE_RD:response=LLC_HIT.HIT_OTHER_CORE_NO_FWD
Counts all demand & prefetch code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded
OFFCORE_RESPONSE:request=ALL_CODE_RD:response=LLC_HIT.NO_SNOOP_NEEDED
Counts all demand & prefetch code reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
OFFCORE_RESPONSE:request=ALL_CODE_RD:response=LLC_HIT.SNOOP_MISS
Counts all demand & prefetch code reads that hit in the L3 and the snoops sent to sibling cores return clean response
OFFCORE_RESPONSE:request=ALL_CODE_RD:response=LLC_MISS.ANY_DRAM
Counts all demand & prefetch code reads that miss the L3 and the data is returned from local or remote dram
OFFCORE_RESPONSE:request=ALL_CODE_RD:response=LLC_MISS.ANY_RESPONSE
Counts all demand & prefetch code reads that miss in the L3
OFFCORE_RESPONSE:request=ALL_CODE_RD:response=LLC_MISS.LOCAL_DRAM
Counts all demand & prefetch code reads that miss the L3 and the data is returned from local dram
OFFCORE_RESPONSE:request=ALL_CODE_RD:response=LLC_MISS.REMOTE_DRAM
Counts all demand & prefetch code reads that miss the L3 and the data is returned from remote dram
OFFCORE_RESPONSE:request=ALL_CODE_RD:response=LLC_MISS.REMOTE_HITM
Counts all demand & prefetch code reads that miss the L3 and the modified data is transferred from remote cache
OFFCORE_RESPONSE:request=ALL_CODE_RD:response=LLC_MISS.REMOTE_HIT_FORWARD
Counts all demand & prefetch code reads that miss the L3 and clean or shared data is transferred from remote cache
OFFCORE_RESPONSE:request=ALL_DATA_RD:response=LLC_HIT.ANY_RESPONSE
Counts all demand & prefetch data reads that hit in the L3
OFFCORE_RESPONSE:request=ALL_DATA_RD:response=LLC_HIT.HITM_OTHER_CORE
Counts all demand & prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
OFFCORE_RESPONSE:request=ALL_DATA_RD:response=LLC_HIT.HIT_OTHER_CORE_NO_FWD
Counts all demand & prefetch data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded
OFFCORE_RESPONSE:request=ALL_DATA_RD:response=LLC_HIT.NO_SNOOP_NEEDED
Counts all demand & prefetch data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
OFFCORE_RESPONSE:request=ALL_DATA_RD:response=LLC_HIT.SNOOP_MISS
Counts all demand & prefetch data reads that hit in the L3 and the snoops sent to sibling cores return clean response
OFFCORE_RESPONSE:request=ALL_DATA_RD:response=LLC_MISS.ANY_DRAM
Counts all demand & prefetch data reads that miss the L3 and the data is returned from local or remote dram
OFFCORE_RESPONSE:request=ALL_DATA_RD:response=LLC_MISS.ANY_RESPONSE
Counts all demand & prefetch data reads that miss in the L3
OFFCORE_RESPONSE:request=ALL_DATA_RD:response=LLC_MISS.LOCAL_DRAM
Counts all demand & prefetch data reads that miss the L3 and the data is returned from local dram
OFFCORE_RESPONSE:request=ALL_DATA_RD:response=LLC_MISS.REMOTE_DRAM
Counts all demand & prefetch data reads that miss the L3 and the data is returned from remote dram
OFFCORE_RESPONSE:request=ALL_DATA_RD:response=LLC_MISS.REMOTE_HITM
Counts all demand & prefetch data reads that miss the L3 and the modified data is transferred from remote cache
OFFCORE_RESPONSE:request=ALL_DATA_RD:response=LLC_MISS.REMOTE_HIT_FORWARD
Counts all demand & prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache
OFFCORE_RESPONSE:request=ALL_PF_CODE_RD:response=LLC_HIT.ANY_RESPONSE
Counts all prefetch code reads that hit in the L3
OFFCORE_RESPONSE:request=ALL_PF_CODE_RD:response=LLC_HIT.HITM_OTHER_CORE
Counts all prefetch code reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
OFFCORE_RESPONSE:request=ALL_PF_CODE_RD:response=LLC_HIT.HIT_OTHER_CORE_NO_FWD
Counts all prefetch code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded
OFFCORE_RESPONSE:request=ALL_PF_CODE_RD:response=LLC_HIT.NO_SNOOP_NEEDED
Counts all prefetch code reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
OFFCORE_RESPONSE:request=ALL_PF_CODE_RD:response=LLC_HIT.SNOOP_MISS
Counts all prefetch code reads that hit in the L3 and the snoops sent to sibling cores return clean response
OFFCORE_RESPONSE:request=ALL_PF_CODE_RD:response=LLC_MISS.ANY_DRAM
Counts all prefetch code reads that miss the L3 and the data is returned from local or remote dram
OFFCORE_RESPONSE:request=ALL_PF_CODE_RD:response=LLC_MISS.ANY_RESPONSE
Counts all prefetch code reads that miss in the L3
OFFCORE_RESPONSE:request=ALL_PF_CODE_RD:response=LLC_MISS.LOCAL_DRAM
Counts all prefetch code reads that miss the L3 and the data is returned from local dram
OFFCORE_RESPONSE:request=ALL_PF_CODE_RD:response=LLC_MISS.REMOTE_DRAM
Counts all prefetch code reads that miss the L3 and the data is returned from remote dram
OFFCORE_RESPONSE:request=ALL_PF_CODE_RD:response=LLC_MISS.REMOTE_HITM
Counts all prefetch code reads that miss the L3 and the modified data is transferred from remote cache
OFFCORE_RESPONSE:request=ALL_PF_CODE_RD:response=LLC_MISS.REMOTE_HIT_FORWARD
Counts all prefetch code reads that miss the L3 and clean or shared data is transferred from remote cache
OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=LLC_HIT.ANY_RESPONSE
Counts all prefetch data reads that hit in the L3
OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=LLC_HIT.HITM_OTHER_CORE
Counts all prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=LLC_HIT.HIT_OTHER_CORE_NO_FWD
Counts all prefetch data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded
OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=LLC_HIT.NO_SNOOP_NEEDED
Counts all prefetch data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=LLC_HIT.SNOOP_MISS
Counts all prefetch data reads that hit in the L3 and the snoops sent to sibling cores return clean response
OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=LLC_MISS.ANY_DRAM
Counts all prefetch data reads that miss the L3 and the data is returned from local or remote dram
OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=LLC_MISS.ANY_RESPONSE
Counts all prefetch data reads that miss in the L3
OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=LLC_MISS.LOCAL_DRAM
Counts all prefetch data reads that miss the L3 and the data is returned from local dram
OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=LLC_MISS.REMOTE_DRAM
Counts all prefetch data reads that miss the L3 and the data is returned from remote dram
OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=LLC_MISS.REMOTE_HITM
Counts all prefetch data reads that miss the L3 and the modified data is transferred from remote cache
OFFCORE_RESPONSE:request=ALL_PF_DATA_RD:response=LLC_MISS.REMOTE_HIT_FORWARD
Counts all prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache
OFFCORE_RESPONSE:request=ALL_PF_RFO:response=LLC_HIT.ANY_RESPONSE
Counts prefetch RFOs that hit in the L3
OFFCORE_RESPONSE:request=ALL_PF_RFO:response=LLC_HIT.HITM_OTHER_CORE
Counts prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
OFFCORE_RESPONSE:request=ALL_PF_RFO:response=LLC_HIT.HIT_OTHER_CORE_NO_FWD
Counts prefetch RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded
OFFCORE_RESPONSE:request=ALL_PF_RFO:response=LLC_HIT.NO_SNOOP_NEEDED
Counts prefetch RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
OFFCORE_RESPONSE:request=ALL_PF_RFO:response=LLC_HIT.SNOOP_MISS
Counts prefetch RFOs that hit in the L3 and the snoops sent to sibling cores return clean response
OFFCORE_RESPONSE:request=ALL_PF_RFO:response=LLC_MISS.ANY_DRAM
Counts prefetch RFOs that miss the L3 and the data is returned from local or remote dram
OFFCORE_RESPONSE:request=ALL_PF_RFO:response=LLC_MISS.ANY_RESPONSE
Counts prefetch RFOs that miss in the L3
OFFCORE_RESPONSE:request=ALL_PF_RFO:response=LLC_MISS.LOCAL_DRAM
Counts prefetch RFOs that miss the L3 and the data is returned from local dram
OFFCORE_RESPONSE:request=ALL_PF_RFO:response=LLC_MISS.REMOTE_DRAM
Counts prefetch RFOs that miss the L3 and the data is returned from remote dram
OFFCORE_RESPONSE:request=ALL_PF_RFO:response=LLC_MISS.REMOTE_HITM
Counts prefetch RFOs that miss the L3 and the modified data is transferred from remote cache
OFFCORE_RESPONSE:request=ALL_PF_RFO:response=LLC_MISS.REMOTE_HIT_FORWARD
Counts prefetch RFOs that miss the L3 and clean or shared data is transferred from remote cache
OFFCORE_RESPONSE:request=ALL_READS:response=LLC_HIT.ANY_RESPONSE
Counts all data/code/rfo reads (demand & prefetch) that hit in the L3
OFFCORE_RESPONSE:request=ALL_READS:response=LLC_HIT.HITM_OTHER_CORE
Counts all data/code/rfo reads (demand & prefetch) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
OFFCORE_RESPONSE:request=ALL_READS:response=LLC_HIT.HIT_OTHER_CORE_NO_FWD
Counts all data/code/rfo reads (demand & prefetch) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded
OFFCORE_RESPONSE:request=ALL_READS:response=LLC_HIT.NO_SNOOP_NEEDED
Counts all data/code/rfo reads (demand & prefetch) that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
OFFCORE_RESPONSE:request=ALL_READS:response=LLC_HIT.SNOOP_MISS
Counts all data/code/rfo reads (demand & prefetch) that hit in the L3 and the snoops sent to sibling cores return clean response
OFFCORE_RESPONSE:request=ALL_READS:response=LLC_MISS.ANY_DRAM
Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the data is returned from local or remote dram
OFFCORE_RESPONSE:request=ALL_READS:response=LLC_MISS.ANY_RESPONSE
Counts all data/code/rfo reads (demand & prefetch) that miss in the L3
OFFCORE_RESPONSE:request=ALL_READS:response=LLC_MISS.LOCAL_DRAM
Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the data is returned from local dram
OFFCORE_RESPONSE:request=ALL_READS:response=LLC_MISS.REMOTE_DRAM
Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the data is returned from remote dram
OFFCORE_RESPONSE:request=ALL_READS:response=LLC_MISS.REMOTE_HITM
Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the modified data is transferred from remote cache
OFFCORE_RESPONSE:request=ALL_READS:response=LLC_MISS.REMOTE_HIT_FORWARD
Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and clean or shared data is transferred from remote cache
OFFCORE_RESPONSE:request=ALL_REQUESTS:response=LLC_HIT.ANY_RESPONSE
Counts all requests that hit in the L3
OFFCORE_RESPONSE:request=ALL_REQUESTS:response=LLC_HIT.HITM_OTHER_CORE
Counts all requests that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
OFFCORE_RESPONSE:request=ALL_REQUESTS:response=LLC_HIT.HIT_OTHER_CORE_NO_FWD
Counts all requests that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded
OFFCORE_RESPONSE:request=ALL_REQUESTS:response=LLC_HIT.NO_SNOOP_NEEDED
Counts all requests that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
OFFCORE_RESPONSE:request=ALL_REQUESTS:response=LLC_HIT.SNOOP_MISS
Counts all requests that hit in the L3 and the snoops sent to sibling cores return clean response
OFFCORE_RESPONSE:request=ALL_REQUESTS:response=LLC_MISS.ANY_DRAM
Counts all requests that miss the L3 and the data is returned from local or remote dram
OFFCORE_RESPONSE:request=ALL_REQUESTS:response=LLC_MISS.ANY_RESPONSE
Counts all requests that miss in the L3
OFFCORE_RESPONSE:request=ALL_REQUESTS:response=LLC_MISS.LOCAL_DRAM
Counts all requests that miss the L3 and the data is returned from local dram
OFFCORE_RESPONSE:request=ALL_REQUESTS:response=LLC_MISS.REMOTE_DRAM
Counts all requests that miss the L3 and the data is returned from remote dram
OFFCORE_RESPONSE:request=ALL_REQUESTS:response=LLC_MISS.REMOTE_HITM
Counts all requests that miss the L3 and the modified data is transferred from remote cache
OFFCORE_RESPONSE:request=ALL_REQUESTS:response=LLC_MISS.REMOTE_HIT_FORWARD
Counts all requests that miss the L3 and clean or shared data is transferred from remote cache
OFFCORE_RESPONSE:request=ALL_RFO:response=LLC_HIT.ANY_RESPONSE
Counts all demand & prefetch RFOs that hit in the L3
OFFCORE_RESPONSE:request=ALL_RFO:response=LLC_HIT.HITM_OTHER_CORE
Counts all demand & prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
OFFCORE_RESPONSE:request=ALL_RFO:response=LLC_HIT.HIT_OTHER_CORE_NO_FWD
Counts all demand & prefetch RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded
OFFCORE_RESPONSE:request=ALL_RFO:response=LLC_HIT.NO_SNOOP_NEEDED
Counts all demand & prefetch RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
OFFCORE_RESPONSE:request=ALL_RFO:response=LLC_HIT.SNOOP_MISS
Counts all demand & prefetch RFOs that hit in the L3 and the snoops sent to sibling cores return clean response
OFFCORE_RESPONSE:request=ALL_RFO:response=LLC_MISS.ANY_DRAM
Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local or remote dram
OFFCORE_RESPONSE:request=ALL_RFO:response=LLC_MISS.ANY_RESPONSE
Counts all demand & prefetch RFOs that miss in the L3
OFFCORE_RESPONSE:request=ALL_RFO:response=LLC_MISS.LOCAL_DRAM
Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local dram
OFFCORE_RESPONSE:request=ALL_RFO:response=LLC_MISS.REMOTE_DRAM
Counts all demand & prefetch RFOs that miss the L3 and the data is returned from remote dram
OFFCORE_RESPONSE:request=ALL_RFO:response=LLC_MISS.REMOTE_HITM
Counts all demand & prefetch RFOs that miss the L3 and the modified data is transferred from remote cache
OFFCORE_RESPONSE:request=ALL_RFO:response=LLC_MISS.REMOTE_HIT_FORWARD
Counts all demand & prefetch RFOs that miss the L3 and clean or shared data is transferred from remote cache
OFFCORE_RESPONSE:request=COREWB:response=LLC_HIT.ANY_RESPONSE
Counts writebacks (modified to exclusive) that hit in the L3
OFFCORE_RESPONSE:request=COREWB:response=LLC_HIT.HITM_OTHER_CORE
Counts writebacks (modified to exclusive) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
OFFCORE_RESPONSE:request=COREWB:response=LLC_HIT.HIT_OTHER_CORE_NO_FWD
Counts writebacks (modified to exclusive) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded
OFFCORE_RESPONSE:request=COREWB:response=LLC_HIT.NO_SNOOP_NEEDED
Counts writebacks (modified to exclusive) that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
OFFCORE_RESPONSE:request=COREWB:response=LLC_HIT.SNOOP_MISS
Counts writebacks (modified to exclusive) that hit in the L3 and the snoops sent to sibling cores return clean response
OFFCORE_RESPONSE:request=COREWB:response=LLC_MISS.ANY_DRAM
Counts writebacks (modified to exclusive) that miss the L3 and the data is returned from local or remote dram
OFFCORE_RESPONSE:request=COREWB:response=LLC_MISS.ANY_RESPONSE
Counts writebacks (modified to exclusive) that miss in the L3
OFFCORE_RESPONSE:request=COREWB:response=LLC_MISS.LOCAL_DRAM
Counts writebacks (modified to exclusive) that miss the L3 and the data is returned from local dram
OFFCORE_RESPONSE:request=COREWB:response=LLC_MISS.REMOTE_DRAM
Counts writebacks (modified to exclusive) that miss the L3 and the data is returned from remote dram
OFFCORE_RESPONSE:request=COREWB:response=LLC_MISS.REMOTE_HITM
Counts writebacks (modified to exclusive) that miss the L3 and the modified data is transferred from remote cache
OFFCORE_RESPONSE:request=COREWB:response=LLC_MISS.REMOTE_HIT_FORWARD
Counts writebacks (modified to exclusive) that miss the L3 and clean or shared data is transferred from remote cache
OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=LLC_HIT.ANY_RESPONSE
Counts all demand code reads that hit in the L3
OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=LLC_HIT.HITM_OTHER_CORE
Counts all demand code reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=LLC_HIT.HIT_OTHER_CORE_NO_FWD
Counts all demand code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded
OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=LLC_HIT.NO_SNOOP_NEEDED
Counts all demand code reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=LLC_HIT.SNOOP_MISS
Counts all demand code reads that hit in the L3 and the snoops sent to sibling cores return clean response
OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=LLC_MISS.ANY_DRAM
Counts all demand code reads that miss the L3 and the data is returned from local or remote dram
OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=LLC_MISS.ANY_RESPONSE
Counts all demand code reads that miss in the L3
OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=LLC_MISS.LOCAL_DRAM
Counts all demand code reads that miss the L3 and the data is returned from local dram
OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=LLC_MISS.REMOTE_DRAM
Counts all demand code reads that miss the L3 and the data is returned from remote dram
OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=LLC_MISS.REMOTE_HITM
Counts all demand code reads that miss the L3 and the modified data is transferred from remote cache
OFFCORE_RESPONSE:request=DEMAND_CODE_RD:response=LLC_MISS.REMOTE_HIT_FORWARD
Counts all demand code reads that miss the L3 and clean or shared data is transferred from remote cache
OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=LLC_HIT.ANY_RESPONSE
Counts demand data reads that hit in the L3
OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=LLC_HIT.HITM_OTHER_CORE
Counts demand data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=LLC_HIT.HIT_OTHER_CORE_NO_FWD
Counts demand data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded
OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=LLC_HIT.NO_SNOOP_NEEDED
Counts demand data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=LLC_HIT.SNOOP_MISS
Counts demand data reads that hit in the L3 and the snoops sent to sibling cores return clean response
OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=LLC_MISS.ANY_DRAM
Counts demand data reads that miss the L3 and the data is returned from local or remote dram
OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=LLC_MISS.ANY_RESPONSE
Counts demand data reads that miss in the L3
OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=LLC_MISS.LOCAL_DRAM
Counts demand data reads that miss the L3 and the data is returned from local dram
OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=LLC_MISS.REMOTE_DRAM
Counts demand data reads that miss the L3 and the data is returned from remote dram
OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=LLC_MISS.REMOTE_HITM
Counts demand data reads that miss the L3 and the modified data is transferred from remote cache
OFFCORE_RESPONSE:request=DEMAND_DATA_RD:response=LLC_MISS.REMOTE_HIT_FORWARD
Counts demand data reads that miss the L3 and clean or shared data is transferred from remote cache
OFFCORE_RESPONSE:request=DEMAND_RFO:response=LLC_HIT.ANY_RESPONSE
Counts all demand data writes (RFOs) that hit in the L3
OFFCORE_RESPONSE:request=DEMAND_RFO:response=LLC_HIT.HITM_OTHER_CORE
Counts all demand data writes (RFOs) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
OFFCORE_RESPONSE:request=DEMAND_RFO:response=LLC_HIT.HIT_OTHER_CORE_NO_FWD
Counts all demand data writes (RFOs) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded
OFFCORE_RESPONSE:request=DEMAND_RFO:response=LLC_HIT.NO_SNOOP_NEEDED
Counts all demand data writes (RFOs) that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
OFFCORE_RESPONSE:request=DEMAND_RFO:response=LLC_HIT.SNOOP_MISS
Counts all demand data writes (RFOs) that hit in the L3 and the snoops sent to sibling cores return clean response
OFFCORE_RESPONSE:request=DEMAND_RFO:response=LLC_MISS.ANY_DRAM
Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local or remote dram
OFFCORE_RESPONSE:request=DEMAND_RFO:response=LLC_MISS.ANY_RESPONSE
Counts all demand data writes (RFOs) that miss in the L3
OFFCORE_RESPONSE:request=DEMAND_RFO:response=LLC_MISS.LOCAL_DRAM
Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local dram
OFFCORE_RESPONSE:request=DEMAND_RFO:response=LLC_MISS.REMOTE_DRAM
Counts all demand data writes (RFOs) that miss the L3 and the data is returned from remote dram
OFFCORE_RESPONSE:request=DEMAND_RFO:response=LLC_MISS.REMOTE_HITM
Counts all demand data writes (RFOs) that miss the L3 and the modified data is transferred from remote cache
OFFCORE_RESPONSE:request=DEMAND_RFO:response=LLC_MISS.REMOTE_HIT_FORWARD
Counts all demand data writes (RFOs) that miss the L3 and clean or shared data is transferred from remote cache
OFFCORE_RESPONSE:request=OTHER:response=LLC_HIT.ANY_RESPONSE
Counts any other requests that hit in the L3
OFFCORE_RESPONSE:request=OTHER:response=LLC_HIT.HITM_OTHER_CORE
Counts any other requests that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
OFFCORE_RESPONSE:request=OTHER:response=LLC_HIT.HIT_OTHER_CORE_NO_FWD
Counts any other requests that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded
OFFCORE_RESPONSE:request=OTHER:response=LLC_HIT.NO_SNOOP_NEEDED
Counts any other requests that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
OFFCORE_RESPONSE:request=OTHER:response=LLC_HIT.SNOOP_MISS
Counts any other requests that hit in the L3 and the snoops sent to sibling cores return clean response
OFFCORE_RESPONSE:request=OTHER:response=LLC_MISS.ANY_DRAM
Counts any other requests that miss the L3 and the data is returned from local or remote dram
OFFCORE_RESPONSE:request=OTHER:response=LLC_MISS.ANY_RESPONSE
Counts any other requests that miss in the L3
OFFCORE_RESPONSE:request=OTHER:response=LLC_MISS.LOCAL_DRAM
Counts any other requests that miss the L3 and the data is returned from local dram
OFFCORE_RESPONSE:request=OTHER:response=LLC_MISS.REMOTE_DRAM
Counts any other requests that miss the L3 and the data is returned from remote dram
OFFCORE_RESPONSE:request=OTHER:response=LLC_MISS.REMOTE_HITM
Counts any other requests that miss the L3 and the modified data is transferred from remote cache
OFFCORE_RESPONSE:request=OTHER:response=LLC_MISS.REMOTE_HIT_FORWARD
Counts any other requests that miss the L3 and clean or shared data is transferred from remote cache
OFFCORE_RESPONSE:request=PF_L2_CODE_RD:response=LLC_HIT.ANY_RESPONSE
Counts all prefetch (that bring data to LLC only) code reads that hit in the L3
OFFCORE_RESPONSE:request=PF_L2_CODE_RD:response=LLC_HIT.HITM_OTHER_CORE
Counts all prefetch (that bring data to LLC only) code reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
OFFCORE_RESPONSE:request=PF_L2_CODE_RD:response=LLC_HIT.HIT_OTHER_CORE_NO_FWD
Counts all prefetch (that bring data to LLC only) code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded
OFFCORE_RESPONSE:request=PF_L2_CODE_RD:response=LLC_HIT.NO_SNOOP_NEEDED
Counts all prefetch (that bring data to LLC only) code reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
OFFCORE_RESPONSE:request=PF_L2_CODE_RD:response=LLC_HIT.SNOOP_MISS
Counts all prefetch (that bring data to LLC only) code reads that hit in the L3 and the snoops sent to sibling cores return clean response
OFFCORE_RESPONSE:request=PF_L2_CODE_RD:response=LLC_MISS.ANY_DRAM
Counts all prefetch (that bring data to LLC only) code reads that miss the L3 and the data is returned from local or remote dram
OFFCORE_RESPONSE:request=PF_L2_CODE_RD:response=LLC_MISS.ANY_RESPONSE
Counts all prefetch (that bring data to LLC only) code reads that miss in the L3
OFFCORE_RESPONSE:request=PF_L2_CODE_RD:response=LLC_MISS.LOCAL_DRAM
Counts all prefetch (that bring data to LLC only) code reads that miss the L3 and the data is returned from local dram
OFFCORE_RESPONSE:request=PF_L2_CODE_RD:response=LLC_MISS.REMOTE_DRAM
Counts all prefetch (that bring data to LLC only) code reads that miss the L3 and the data is returned from remote dram
OFFCORE_RESPONSE:request=PF_L2_CODE_RD:response=LLC_MISS.REMOTE_HITM
Counts all prefetch (that bring data to LLC only) code reads that miss the L3 and the modified data is transferred from remote cache
OFFCORE_RESPONSE:request=PF_L2_CODE_RD:response=LLC_MISS.REMOTE_HIT_FORWARD
Counts all prefetch (that bring data to LLC only) code reads that miss the L3 and clean or shared data is transferred from remote cache
OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=LLC_HIT.ANY_RESPONSE
Counts prefetch (that bring data to L2) data reads that hit in the L3
OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=LLC_HIT.HITM_OTHER_CORE
Counts prefetch (that bring data to L2) data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=LLC_HIT.HIT_OTHER_CORE_NO_FWD
Counts prefetch (that bring data to L2) data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded
OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=LLC_HIT.NO_SNOOP_NEEDED
Counts prefetch (that bring data to L2) data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=LLC_HIT.SNOOP_MISS
Counts prefetch (that bring data to L2) data reads that hit in the L3 and the snoops sent to sibling cores return clean response
OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=LLC_MISS.ANY_DRAM
Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from local or remote dram
OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=LLC_MISS.ANY_RESPONSE
Counts prefetch (that bring data to L2) data reads that miss in the L3
OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=LLC_MISS.LOCAL_DRAM
Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from local dram
OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=LLC_MISS.REMOTE_DRAM
Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from remote dram
OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=LLC_MISS.REMOTE_HITM
Counts prefetch (that bring data to L2) data reads that miss the L3 and the modified data is transferred from remote cache
OFFCORE_RESPONSE:request=PF_L2_DATA_RD:response=LLC_MISS.REMOTE_HIT_FORWARD
Counts prefetch (that bring data to L2) data reads that miss the L3 and clean or shared data is transferred from remote cache
OFFCORE_RESPONSE:request=PF_L2_RFO:response=LLC_HIT.ANY_RESPONSE
Counts all prefetch (that bring data to L2) RFOs that hit in the L3
OFFCORE_RESPONSE:request=PF_L2_RFO:response=LLC_HIT.HITM_OTHER_CORE
Counts all prefetch (that bring data to L2) RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
OFFCORE_RESPONSE:request=PF_L2_RFO:response=LLC_HIT.HIT_OTHER_CORE_NO_FWD
Counts all prefetch (that bring data to L2) RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded
OFFCORE_RESPONSE:request=PF_L2_RFO:response=LLC_HIT.NO_SNOOP_NEEDED
Counts all prefetch (that bring data to L2) RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
OFFCORE_RESPONSE:request=PF_L2_RFO:response=LLC_HIT.SNOOP_MISS
Counts all prefetch (that bring data to L2) RFOs that hit in the L3 and the snoops sent to sibling cores return clean response
OFFCORE_RESPONSE:request=PF_L2_RFO:response=LLC_MISS.ANY_DRAM
Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from local or remote dram
OFFCORE_RESPONSE:request=PF_L2_RFO:response=LLC_MISS.ANY_RESPONSE
Counts all prefetch (that bring data to L2) RFOs that miss in the L3
OFFCORE_RESPONSE:request=PF_L2_RFO:response=LLC_MISS.LOCAL_DRAM
Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from local dram
OFFCORE_RESPONSE:request=PF_L2_RFO:response=LLC_MISS.REMOTE_DRAM
Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from remote dram
OFFCORE_RESPONSE:request=PF_L2_RFO:response=LLC_MISS.REMOTE_HITM
Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the modified data is transferred from remote cache
OFFCORE_RESPONSE:request=PF_L2_RFO:response=LLC_MISS.REMOTE_HIT_FORWARD
Counts all prefetch (that bring data to L2) RFOs that miss the L3 and clean or shared data is transferred from remote cache
OFFCORE_RESPONSE:request=PF_LLC_CODE_RD:response=LLC_HIT.ANY_RESPONSE
Counts prefetch (that bring data to LLC only) code reads that hit in the L3
OFFCORE_RESPONSE:request=PF_LLC_CODE_RD:response=LLC_HIT.HITM_OTHER_CORE
Counts prefetch (that bring data to LLC only) code reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
OFFCORE_RESPONSE:request=PF_LLC_CODE_RD:response=LLC_HIT.HIT_OTHER_CORE_NO_FWD
Counts prefetch (that bring data to LLC only) code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded
OFFCORE_RESPONSE:request=PF_LLC_CODE_RD:response=LLC_HIT.NO_SNOOP_NEEDED
Counts prefetch (that bring data to LLC only) code reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
OFFCORE_RESPONSE:request=PF_LLC_CODE_RD:response=LLC_HIT.SNOOP_MISS
Counts prefetch (that bring data to LLC only) code reads that hit in the L3 and the snoops sent to sibling cores return clean response
OFFCORE_RESPONSE:request=PF_LLC_CODE_RD:response=LLC_MISS.ANY_DRAM
Counts prefetch (that bring data to LLC only) code reads that miss the L3 and the data is returned from local or remote dram
OFFCORE_RESPONSE:request=PF_LLC_CODE_RD:response=LLC_MISS.ANY_RESPONSE
Counts prefetch (that bring data to LLC only) code reads that miss in the L3
OFFCORE_RESPONSE:request=PF_LLC_CODE_RD:response=LLC_MISS.LOCAL_DRAM
Counts prefetch (that bring data to LLC only) code reads that miss the L3 and the data is returned from local dram
OFFCORE_RESPONSE:request=PF_LLC_CODE_RD:response=LLC_MISS.REMOTE_DRAM
Counts prefetch (that bring data to LLC only) code reads that miss the L3 and the data is returned from remote dram
OFFCORE_RESPONSE:request=PF_LLC_CODE_RD:response=LLC_MISS.REMOTE_HITM
Counts prefetch (that bring data to LLC only) code reads that miss the L3 and the modified data is transferred from remote cache
OFFCORE_RESPONSE:request=PF_LLC_CODE_RD:response=LLC_MISS.REMOTE_HIT_FORWARD
Counts prefetch (that bring data to LLC only) code reads that miss the L3 and clean or shared data is transferred from remote cache
OFFCORE_RESPONSE:request=PF_LLC_DATA_RD:response=LLC_HIT.ANY_RESPONSE
Counts all prefetch (that bring data to LLC only) data reads that hit in the L3
OFFCORE_RESPONSE:request=PF_LLC_DATA_RD:response=LLC_HIT.HITM_OTHER_CORE
Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
OFFCORE_RESPONSE:request=PF_LLC_DATA_RD:response=LLC_HIT.HIT_OTHER_CORE_NO_FWD
Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded
OFFCORE_RESPONSE:request=PF_LLC_DATA_RD:response=LLC_HIT.NO_SNOOP_NEEDED
Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
OFFCORE_RESPONSE:request=PF_LLC_DATA_RD:response=LLC_HIT.SNOOP_MISS
Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 and the snoops sent to sibling cores return clean response
OFFCORE_RESPONSE:request=PF_LLC_DATA_RD:response=LLC_MISS.ANY_DRAM
Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from local or remote dram
OFFCORE_RESPONSE:request=PF_LLC_DATA_RD:response=LLC_MISS.ANY_RESPONSE
Counts all prefetch (that bring data to LLC only) data reads that miss in the L3
OFFCORE_RESPONSE:request=PF_LLC_DATA_RD:response=LLC_MISS.LOCAL_DRAM
Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from local dram
OFFCORE_RESPONSE:request=PF_LLC_DATA_RD:response=LLC_MISS.REMOTE_DRAM
Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from remote dram
OFFCORE_RESPONSE:request=PF_LLC_DATA_RD:response=LLC_MISS.REMOTE_HITM
Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the modified data is transferred from remote cache
OFFCORE_RESPONSE:request=PF_LLC_DATA_RD:response=LLC_MISS.REMOTE_HIT_FORWARD
Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and clean or shared data is transferred from remote cache
OFFCORE_RESPONSE:request=PF_LLC_RFO:response=LLC_HIT.ANY_RESPONSE
Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3
OFFCORE_RESPONSE:request=PF_LLC_RFO:response=LLC_HIT.HITM_OTHER_CORE
Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
OFFCORE_RESPONSE:request=PF_LLC_RFO:response=LLC_HIT.HIT_OTHER_CORE_NO_FWD
Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded
OFFCORE_RESPONSE:request=PF_LLC_RFO:response=LLC_HIT.NO_SNOOP_NEEDED
Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
OFFCORE_RESPONSE:request=PF_LLC_RFO:response=LLC_HIT.SNOOP_MISS
Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 and the snoops sent to sibling cores return clean response
OFFCORE_RESPONSE:request=PF_LLC_RFO:response=LLC_MISS.ANY_DRAM
Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from local or remote dram
OFFCORE_RESPONSE:request=PF_LLC_RFO:response=LLC_MISS.ANY_RESPONSE
Counts all prefetch (that bring data to LLC only) RFOs that miss in the L3
OFFCORE_RESPONSE:request=PF_LLC_RFO:response=LLC_MISS.LOCAL_DRAM
Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from local dram
OFFCORE_RESPONSE:request=PF_LLC_RFO:response=LLC_MISS.REMOTE_DRAM
Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from remote dram
OFFCORE_RESPONSE:request=PF_LLC_RFO:response=LLC_MISS.REMOTE_HITM
Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the modified data is transferred from remote cache
OFFCORE_RESPONSE:request=PF_LLC_RFO:response=LLC_MISS.REMOTE_HIT_FORWARD
Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and clean or shared data is transferred from remote cache
OTHER_ASSISTS.ANY_WB_ASSIST
Number of times any microcode assist is invoked by HW upon uop writeback.
OTHER_ASSISTS.AVX_TO_SSE
Number of transitions from AVX-256 to legacy SSE when penalty applicable.
OTHER_ASSISTS.SSE_TO_AVX
Number of transitions from SSE to AVX-256 when penalty applicable.
PAGE_WALKER_LOADS.DTLB_L1
Number of DTLB page walker hits in the L1+FB
PAGE_WALKER_LOADS.DTLB_L2
Number of DTLB page walker hits in the L2
PAGE_WALKER_LOADS.DTLB_L3
Number of DTLB page walker hits in the L3 + XSNP
PAGE_WALKER_LOADS.DTLB_MEMORY
Number of DTLB page walker hits in Memory
PAGE_WALKER_LOADS.EPT_DTLB_L1
Counts the number of Extended Page Table walks from the DTLB that hit in the L1 and FB.
PAGE_WALKER_LOADS.EPT_DTLB_L2
Counts the number of Extended Page Table walks from the DTLB that hit in the L2.
PAGE_WALKER_LOADS.EPT_DTLB_L3
Counts the number of Extended Page Table walks from the DTLB that hit in the L3.
PAGE_WALKER_LOADS.EPT_DTLB_MEMORY
Counts the number of Extended Page Table walks from the DTLB that hit in memory.
PAGE_WALKER_LOADS.EPT_ITLB_L1
Counts the number of Extended Page Table walks from the ITLB that hit in the L1 and FB.
PAGE_WALKER_LOADS.EPT_ITLB_L2
Counts the number of Extended Page Table walks from the ITLB that hit in the L2.
PAGE_WALKER_LOADS.EPT_ITLB_L3
Counts the number of Extended Page Table walks from the ITLB that hit in the L2.
PAGE_WALKER_LOADS.EPT_ITLB_MEMORY
Counts the number of Extended Page Table walks from the ITLB that hit in memory.
PAGE_WALKER_LOADS.ITLB_L1
Number of ITLB page walker hits in the L1+FB
PAGE_WALKER_LOADS.ITLB_L2
Number of ITLB page walker hits in the L2
PAGE_WALKER_LOADS.ITLB_L3
Number of ITLB page walker hits in the L3 + XSNP
PAGE_WALKER_LOADS.ITLB_MEMORY
Number of ITLB page walker hits in Memory
RESOURCE_STALLS.ANY
Resource-related stall cycles
RESOURCE_STALLS.ROB
Cycles stalled due to re-order buffer full.
RESOURCE_STALLS.RS
Cycles stalled due to no eligible RS entry available.
RESOURCE_STALLS.SB
This event counts cycles during which no instructions were allocated because no Store Buffers (SB) were available.
ROB_MISC_EVENTS.LBR_INSERTS
Count cases of saving new LBR
RS_EVENTS.EMPTY_CYCLES
This event counts cycles when the Reservation Station ( RS ) is empty for the thread. The RS is a structure that buffers allocated micro-ops from the Front-end. If there are many cycles when the RS is empty, it may represent an underflow of instructions delivered from the Front-end.
RS_EVENTS.EMPTY_END
Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.
RTM_RETIRED.ABORTED
Number of times an RTM execution aborted due to any reasons (multiple categories may count as one).
RTM_RETIRED.ABORTED_MISC1
Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)
RTM_RETIRED.ABORTED_MISC2
Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).
RTM_RETIRED.ABORTED_MISC3
Number of times an RTM execution aborted due to HLE-unfriendly instructions
RTM_RETIRED.ABORTED_MISC4
Number of times an RTM execution aborted due to incompatible memory type
RTM_RETIRED.ABORTED_MISC5
Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)
RTM_RETIRED.ABORTED_PS
Number of times an RTM execution aborted due to any reasons (multiple categories may count as one).
RTM_RETIRED.COMMIT
Number of times an RTM execution successfully committed
RTM_RETIRED.START
Number of times an RTM execution started.
TLB_FLUSH.DTLB_THREAD
DTLB flush attempts of the thread-specific entries
TLB_FLUSH.STLB_ANY
STLB flush attempts
TX_EXEC.MISC1
Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.
TX_EXEC.MISC2
Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region
TX_EXEC.MISC3
Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded
TX_EXEC.MISC4
Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.
TX_EXEC.MISC5
Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region
TX_MEM.ABORT_CAPACITY_WRITE
Number of times a transactional abort was signaled due to a data capacity limitation for transactional writes.
TX_MEM.ABORT_CONFLICT
Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address
TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH
Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer
TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY
Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.
TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT
Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.
TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK
Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer
TX_MEM.HLE_ELISION_BUFFER_FULL
Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.
UNC_C_BOUNCE_CONTROL
Bounce Control
UNC_C_CLOCKTICKS
Uncore Clocks
UNC_C_COUNTER0_OCCUPANCY
Counter 0 Occupancy
UNC_C_FAST_ASSERTED
FaST wire asserted
UNC_C_LLC_LOOKUP.ANY
Any Request
UNC_C_LLC_LOOKUP.DATA_READ
Data Read Request
UNC_C_LLC_LOOKUP.NID
Lookups that Match NID
UNC_C_LLC_LOOKUP.READ
Any Read Request
UNC_C_LLC_LOOKUP.REMOTE_SNOOP
External Snoop Request
UNC_C_LLC_LOOKUP.WRITE
Write Requests
UNC_C_LLC_VICTIMS.E_STATE
Lines in E state
UNC_C_LLC_VICTIMS.F_STATE
Lines Victimized
UNC_C_LLC_VICTIMS.I_STATE
Lines in S State
UNC_C_LLC_VICTIMS.MISS
Lines Victimized
UNC_C_LLC_VICTIMS.M_STATE
Lines in M state
UNC_C_LLC_VICTIMS.NID
Victimized Lines that Match NID
UNC_C_LLC_VICTIMS.S_STATE
Lines in S State
UNC_C_MISC.CVZERO_PREFETCH_MISS
DRd hitting non-M with raw CV=0
UNC_C_MISC.CVZERO_PREFETCH_VICTIM
Clean Victim with raw CV=0
UNC_C_MISC.RFO_HIT_S
RFO HitS
UNC_C_MISC.RSPI_WAS_FSE
Silent Snoop Eviction
UNC_C_MISC.STARTED
Cbo Misc
UNC_C_MISC.WC_ALIASING
Write Combining Aliasing
UNC_C_QLRU.AGE0
LRU Age 0
UNC_C_QLRU.AGE1
LRU Age 1
UNC_C_QLRU.AGE2
LRU Age 2
UNC_C_QLRU.AGE3
LRU Age 3
UNC_C_QLRU.LRU_DECREMENT
LRU Bits Decremented
UNC_C_QLRU.VICTIM_NON_ZERO
Non-0 Aged Victim
UNC_C_RING_AD_USED.ALL
All
UNC_C_RING_AD_USED.DOWN
Down
UNC_C_RING_AD_USED.DOWN_EVEN
Down and Even
UNC_C_RING_AD_USED.DOWN_ODD
Down and Odd
UNC_C_RING_AD_USED.UP_EVEN
Up and Even
UNC_C_RING_AD_USED.UP_ODD
Up and Odd
UNC_C_RING_AK_USED.ALL
All
UNC_C_RING_AK_USED.DOWN
Down
UNC_C_RING_AK_USED.DOWN_EVEN
Down and Even
UNC_C_RING_AK_USED.DOWN_ODD
Down and Odd
UNC_C_RING_AK_USED.UP_EVEN
Up and Even
UNC_C_RING_AK_USED.UP_ODD
Up and Odd
UNC_C_RING_BL_USED.ALL
Down
UNC_C_RING_BL_USED.DOWN
Down
UNC_C_RING_BL_USED.DOWN_EVEN
Down and Even
UNC_C_RING_BL_USED.DOWN_ODD
Down and Odd
UNC_C_RING_BL_USED.UP_EVEN
Up and Even
UNC_C_RING_BL_USED.UP_ODD
Up and Odd
UNC_C_RING_BOUNCES.IV
Snoops of processor's cache.
UNC_C_RING_IV_USED.ANY
Any
UNC_C_RING_IV_USED.DN
Any
UNC_C_RING_IV_USED.DOWN
Down
UNC_C_RING_IV_USED.UP
Any
UNC_C_RING_SINK_STARVED.AD
AD
UNC_C_RING_SINK_STARVED.AK
AK
UNC_C_RING_SINK_STARVED.BL
BL
UNC_C_RING_SINK_STARVED.IV
IV
UNC_C_RING_SRC_THRTL
Number of cycles the Cbo is actively throttling traffic onto the Ring in order to limit bounce traffic.
UNC_C_RxR_EXT_STARVED.IPQ
IRQ
UNC_C_RxR_EXT_STARVED.IRQ
IPQ
UNC_C_RxR_EXT_STARVED.ISMQ_BIDS
ISMQ_BID
UNC_C_RxR_EXT_STARVED.PRQ
PRQ
UNC_C_RxR_INSERTS.IPQ
IPQ
UNC_C_RxR_INSERTS.IRQ
IRQ
UNC_C_RxR_INSERTS.IRQ_REJ
IRQ Rejected
UNC_C_RxR_INSERTS.PRQ
PRQ
UNC_C_RxR_INSERTS.PRQ_REJ
PRQ
UNC_C_RxR_INT_STARVED.IPQ
IPQ
UNC_C_RxR_INT_STARVED.IRQ
IRQ
UNC_C_RxR_INT_STARVED.ISMQ
ISMQ
UNC_C_RxR_INT_STARVED.PRQ
PRQ
UNC_C_RxR_IPQ_RETRY.ADDR_CONFLICT
Address Conflict
UNC_C_RxR_IPQ_RETRY.ANY
Any Reject
UNC_C_RxR_IPQ_RETRY.FULL
No Egress Credits
UNC_C_RxR_IPQ_RETRY.QPI_CREDITS
No QPI Credits
UNC_C_RxR_IPQ_RETRY2.AD_SBO
No AD Sbo Credits
UNC_C_RxR_IPQ_RETRY2.TARGET
Target Node Filter
UNC_C_RxR_IRQ_RETRY.ADDR_CONFLICT
Address Conflict
UNC_C_RxR_IRQ_RETRY.ANY
Any Reject
UNC_C_RxR_IRQ_RETRY.FULL
No Egress Credits
UNC_C_RxR_IRQ_RETRY.IIO_CREDITS
No IIO Credits
UNC_C_RxR_IRQ_RETRY.NID
Ingress Request Queue Rejects
UNC_C_RxR_IRQ_RETRY.QPI_CREDITS
No QPI Credits
UNC_C_RxR_IRQ_RETRY.RTID
No RTIDs
UNC_C_RxR_IRQ_RETRY2.AD_SBO
No AD Sbo Credits
UNC_C_RxR_IRQ_RETRY2.BL_SBO
No BL Sbo Credits
UNC_C_RxR_IRQ_RETRY2.TARGET
Target Node Filter
UNC_C_RxR_ISMQ_RETRY.ANY
Any Reject
UNC_C_RxR_ISMQ_RETRY.FULL
No Egress Credits
UNC_C_RxR_ISMQ_RETRY.IIO_CREDITS
No IIO Credits
UNC_C_RxR_ISMQ_RETRY.NID
ISMQ Retries
UNC_C_RxR_ISMQ_RETRY.QPI_CREDITS
No QPI Credits
UNC_C_RxR_ISMQ_RETRY.RTID
No RTIDs
UNC_C_RxR_ISMQ_RETRY.WB_CREDITS
ISMQ Retries
UNC_C_RxR_ISMQ_RETRY2.AD_SBO
No AD Sbo Credits
UNC_C_RxR_ISMQ_RETRY2.BL_SBO
No BL Sbo Credits
UNC_C_RxR_ISMQ_RETRY2.TARGET
Target Node Filter
UNC_C_RxR_OCCUPANCY.IPQ
IPQ
UNC_C_RxR_OCCUPANCY.IRQ
IRQ
UNC_C_RxR_OCCUPANCY.IRQ_REJ
IRQ Rejected
UNC_C_RxR_OCCUPANCY.IRQ_REJECTED
IRQ Rejected
UNC_C_RxR_OCCUPANCY.PRQ_REJ
PRQ Rejects
UNC_C_SBO_CREDITS_ACQUIRED.AD
For AD Ring
UNC_C_SBO_CREDITS_ACQUIRED.BL
For BL Ring
UNC_C_SBO_CREDIT_OCCUPANCY.AD
For AD Ring
UNC_C_SBO_CREDIT_OCCUPANCY.BL
For BL Ring
UNC_C_TOR_INSERTS.ALL
All
UNC_C_TOR_INSERTS.EVICTION
Evictions
UNC_C_TOR_INSERTS.LOCAL
Local Memory
UNC_C_TOR_INSERTS.LOCAL_OPCODE
Local Memory - Opcode Matched
UNC_C_TOR_INSERTS.MISS_LOCAL
Misses to Local Memory
UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE
Misses to Local Memory - Opcode Matched
UNC_C_TOR_INSERTS.MISS_OPCODE
Miss Opcode Match
UNC_C_TOR_INSERTS.MISS_REMOTE
Misses to Remote Memory
UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE
Misses to Remote Memory - Opcode Matched
UNC_C_TOR_INSERTS.NID_ALL
NID Matched
UNC_C_TOR_INSERTS.NID_EVICTION
NID Matched Evictions
UNC_C_TOR_INSERTS.NID_MISS_ALL
NID Matched Miss All
UNC_C_TOR_INSERTS.NID_MISS_OPCODE
NID and Opcode Matched Miss
UNC_C_TOR_INSERTS.NID_OPCODE
NID and Opcode Matched
UNC_C_TOR_INSERTS.NID_WB
NID Matched Writebacks
UNC_C_TOR_INSERTS.OPCODE
Opcode Match
UNC_C_TOR_INSERTS.REMOTE
Remote Memory
UNC_C_TOR_INSERTS.REMOTE_OPCODE
Remote Memory - Opcode Matched
UNC_C_TOR_INSERTS.WB
Writebacks
UNC_C_TOR_OCCUPANCY.ALL
Any
UNC_C_TOR_OCCUPANCY.EVICTION
Evictions
UNC_C_TOR_OCCUPANCY.LOCAL
TOR Occupancy
UNC_C_TOR_OCCUPANCY.LOCAL_OPCODE
Local Memory - Opcode Matched
UNC_C_TOR_OCCUPANCY.MISS_ALL
Miss All
UNC_C_TOR_OCCUPANCY.MISS_LOCAL
TOR Occupancy
UNC_C_TOR_OCCUPANCY.MISS_LOCAL_OPCODE
Misses to Local Memory - Opcode Matched
UNC_C_TOR_OCCUPANCY.MISS_OPCODE
Miss Opcode Match
UNC_C_TOR_OCCUPANCY.MISS_REMOTE
TOR Occupancy
UNC_C_TOR_OCCUPANCY.MISS_REMOTE_OPCODE
Misses to Remote Memory - Opcode Matched
UNC_C_TOR_OCCUPANCY.NID_ALL
NID Matched
UNC_C_TOR_OCCUPANCY.NID_EVICTION
NID Matched Evictions
UNC_C_TOR_OCCUPANCY.NID_MISS_ALL
NID Matched
UNC_C_TOR_OCCUPANCY.NID_MISS_OPCODE
NID and Opcode Matched Miss
UNC_C_TOR_OCCUPANCY.NID_OPCODE
NID and Opcode Matched
UNC_C_TOR_OCCUPANCY.NID_WB
NID Matched Writebacks
UNC_C_TOR_OCCUPANCY.OPCODE
Opcode Match
UNC_C_TOR_OCCUPANCY.REMOTE
TOR Occupancy
UNC_C_TOR_OCCUPANCY.REMOTE_OPCODE
Remote Memory - Opcode Matched
UNC_C_TOR_OCCUPANCY.WB
Writebacks
UNC_C_TxR_ADS_USED.AD
Onto AD Ring
UNC_C_TxR_ADS_USED.AK
Onto AK Ring
UNC_C_TxR_ADS_USED.BL
Onto BL Ring
UNC_C_TxR_INSERTS.AD_CACHE
AD - Cachebo
UNC_C_TxR_INSERTS.AD_CORE
AD - Corebo
UNC_C_TxR_INSERTS.AK_CACHE
AK - Cachebo
UNC_C_TxR_INSERTS.AK_CORE
AK - Corebo
UNC_C_TxR_INSERTS.BL_CACHE
BL - Cacheno
UNC_C_TxR_INSERTS.BL_CORE
BL - Corebo
UNC_C_TxR_INSERTS.IV_CACHE
IV - Cachebo
UNC_C_TxR_STARVED.AD_CORE
Onto AD Ring (to core)
UNC_C_TxR_STARVED.AK_BOTH
Onto AK Ring
UNC_C_TxR_STARVED.BL_BOTH
Onto BL Ring
UNC_C_TxR_STARVED.IV
Onto IV Ring
UNC_H_ADDR_OPC_MATCH.AD
AD Opcodes
UNC_H_ADDR_OPC_MATCH.ADDR
Address
UNC_H_ADDR_OPC_MATCH.AK
AK Opcodes
UNC_H_ADDR_OPC_MATCH.BL
BL Opcodes
UNC_H_ADDR_OPC_MATCH.FILT
Address & Opcode Match
UNC_H_ADDR_OPC_MATCH.OPC
Opcode
UNC_H_BT_CYCLES_NE
BT Cycles Not Empty
UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_BL_HAZARD
Incoming Data Hazard
UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_SNP_HAZARD
Incoming Snoop Hazard
UNC_H_BT_TO_HT_NOT_ISSUED.RSPACKCFLT_HAZARD
Incoming Data Hazard
UNC_H_BT_TO_HT_NOT_ISSUED.WBMDATA_HAZARD
Incoming Data Hazard
UNC_H_BYPASS_IMC.NOT_TAKEN
Not Taken
UNC_H_BYPASS_IMC.TAKEN
Taken
UNC_H_DIRECT2CORE_COUNT
Direct2Core Messages Sent
UNC_H_DIRECT2CORE_CYCLES_DISABLED
Cycles when Direct2Core was Disabled
UNC_H_DIRECT2CORE_TXN_OVERRIDE
Number of Reads that had Direct2Core Overridden
UNC_H_DIRECTORY_LAT_OPT
Directory Lat Opt Return
UNC_H_DIRECTORY_LOOKUP.NO_SNP
Snoop Not Needed
UNC_H_DIRECTORY_LOOKUP.SNP
Snoop Needed
UNC_H_DIRECTORY_UPDATE.ANY
Any Directory Update
UNC_H_DIRECTORY_UPDATE.CLEAR
Directory Clear
UNC_H_DIRECTORY_UPDATE.SET
Directory Set
UNC_H_HITME_HIT.ACKCNFLTWBI
op is AckCnfltWbI
UNC_H_HITME_HIT.ALL
All Requests
UNC_H_HITME_HIT.ALLOCS
Allocations
UNC_H_HITME_HIT.EVICTS
Allocations
UNC_H_HITME_HIT.HOM
HOM Requests
UNC_H_HITME_HIT.INVALS
Invalidations
UNC_H_HITME_HIT.READ_OR_INVITOE
op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE
UNC_H_HITME_HIT.RSP
op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI
UNC_H_HITME_HIT.RSPFWDI_LOCAL
op is RspIFwd or RspIFwdWb for a local request
UNC_H_HITME_HIT.RSPFWDI_REMOTE
op is RspIFwd or RspIFwdWb for a remote request
UNC_H_HITME_HIT.RSPFWDS
op is RsSFwd or RspSFwdWb
UNC_H_HITME_HIT.WBMTOE_OR_S
op is WbMtoE or WbMtoS
UNC_H_HITME_HIT.WBMTOI
op is WbMtoI
UNC_H_HITME_HIT_PV_BITS_SET.ACKCNFLTWBI
op is AckCnfltWbI
UNC_H_HITME_HIT_PV_BITS_SET.ALL
All Requests
UNC_H_HITME_HIT_PV_BITS_SET.HOM
HOM Requests
UNC_H_HITME_HIT_PV_BITS_SET.READ_OR_INVITOE
op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE
UNC_H_HITME_HIT_PV_BITS_SET.RSP
op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI
UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDI_LOCAL
op is RspIFwd or RspIFwdWb for a local request
UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDI_REMOTE
op is RspIFwd or RspIFwdWb for a remote request
UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDS
op is RsSFwd or RspSFwdWb
UNC_H_HITME_HIT_PV_BITS_SET.WBMTOE_OR_S
op is WbMtoE or WbMtoS
UNC_H_HITME_HIT_PV_BITS_SET.WBMTOI
op is WbMtoI
UNC_H_HITME_LOOKUP.ACKCNFLTWBI
op is AckCnfltWbI
UNC_H_HITME_LOOKUP.ALL
All Requests
UNC_H_HITME_LOOKUP.ALLOCS
Allocations
UNC_H_HITME_LOOKUP.HOM
HOM Requests
UNC_H_HITME_LOOKUP.INVALS
Invalidations
UNC_H_HITME_LOOKUP.READ_OR_INVITOE
op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE
UNC_H_HITME_LOOKUP.RSP
op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI
UNC_H_HITME_LOOKUP.RSPFWDI_LOCAL
op is RspIFwd or RspIFwdWb for a local request
UNC_H_HITME_LOOKUP.RSPFWDI_REMOTE
op is RspIFwd or RspIFwdWb for a remote request
UNC_H_HITME_LOOKUP.RSPFWDS
op is RsSFwd or RspSFwdWb
UNC_H_HITME_LOOKUP.WBMTOE_OR_S
op is WbMtoE or WbMtoS
UNC_H_HITME_LOOKUP.WBMTOI
op is WbMtoI
UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI0
AD to QPI Link 0
UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI1
AD to QPI Link 1
UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI2
BL to QPI Link 0
UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI0
BL to QPI Link 0
UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI1
BL to QPI Link 1
UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI2
BL to QPI Link 1
UNC_H_IMC_READS.NORMAL
Normal Priority
UNC_H_IMC_RETRY
Retry Events
UNC_H_IMC_WRITES.ALL
All Writes
UNC_H_IMC_WRITES.FULL
Full Line Non-ISOCH
UNC_H_IMC_WRITES.FULL_ISOCH
ISOCH Full Line
UNC_H_IMC_WRITES.PARTIAL
Partial Non-ISOCH
UNC_H_IMC_WRITES.PARTIAL_ISOCH
ISOCH Partial
UNC_H_IOT_BACKPRESSURE.HUB
IOT Backpressure
UNC_H_IOT_BACKPRESSURE.SAT
IOT Backpressure
UNC_H_IOT_CTS_EAST_LO.CTS0
IOT Common Trigger Sequencer - Lo
UNC_H_IOT_CTS_EAST_LO.CTS1
IOT Common Trigger Sequencer - Lo
UNC_H_IOT_CTS_HI.CTS2
IOT Common Trigger Sequencer - Hi
UNC_H_IOT_CTS_HI.CTS3
IOT Common Trigger Sequencer - Hi
UNC_H_IOT_CTS_WEST_LO.CTS0
IOT Common Trigger Sequencer - Lo
UNC_H_IOT_CTS_WEST_LO.CTS1
IOT Common Trigger Sequencer - Lo
UNC_H_OSB.CANCELLED
Cancelled
UNC_H_OSB.INVITOE_LOCAL
Local InvItoE
UNC_H_OSB.READS_LOCAL
Local Reads
UNC_H_OSB.READS_LOCAL_USEFUL
Reads Local - Useful
UNC_H_OSB.REMOTE_USEFUL
Remote - Useful
UNC_H_OSB_EDR.READS_LOCAL_I
Reads to Local I
UNC_H_OSB_EDR.READS_LOCAL_S
Reads to Local S
UNC_H_OSB_EDR.READS_REMOTE_I
Reads to Remote I
UNC_H_OSB_EDR.READS_REMOTE_S
Reads to Remote S
UNC_H_REQUESTS.INVITOE_LOCAL
Local InvItoEs
UNC_H_REQUESTS.INVITOE_REMOTE
Remote InvItoEs
UNC_H_REQUESTS.READS
Reads
UNC_H_REQUESTS.READS_LOCAL
Local Reads
UNC_H_REQUESTS.READS_REMOTE
Remote Reads
UNC_H_REQUESTS.WRITES
Writes
UNC_H_REQUESTS.WRITES_LOCAL
Local Writes
UNC_H_REQUESTS.WRITES_REMOTE
Remote Writes
UNC_H_RING_AD_USED.CCW
Counterclockwise
UNC_H_RING_AD_USED.CCW_EVEN
Counterclockwise and Even
UNC_H_RING_AD_USED.CCW_ODD
Counterclockwise and Odd
UNC_H_RING_AD_USED.CW
Clockwise
UNC_H_RING_AD_USED.CW_EVEN
Clockwise and Even
UNC_H_RING_AD_USED.CW_ODD
Clockwise and Odd
UNC_H_RING_AK_USED.CCW
Counterclockwise
UNC_H_RING_AK_USED.CCW_EVEN
Counterclockwise and Even
UNC_H_RING_AK_USED.CCW_ODD
Counterclockwise and Odd
UNC_H_RING_AK_USED.CW
Clockwise
UNC_H_RING_AK_USED.CW_EVEN
Clockwise and Even
UNC_H_RING_AK_USED.CW_ODD
Clockwise and Odd
UNC_H_RING_BL_USED.CCW
Counterclockwise
UNC_H_RING_BL_USED.CCW_EVEN
Counterclockwise and Even
UNC_H_RING_BL_USED.CCW_ODD
Counterclockwise and Odd
UNC_H_RING_BL_USED.CW
Clockwise
UNC_H_RING_BL_USED.CW_EVEN
Clockwise and Even
UNC_H_RING_BL_USED.CW_ODD
Clockwise and Odd
UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN0
Channel 0
UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN1
Channel 1
UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN2
Channel 2
UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN3
Channel 3
UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN0
Channel 0
UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN1
Channel 1
UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN2
Channel 2
UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN3
Channel 3
UNC_H_SBO0_CREDITS_ACQUIRED.AD
For AD Ring
UNC_H_SBO0_CREDITS_ACQUIRED.BL
For BL Ring
UNC_H_SBO0_CREDIT_OCCUPANCY.AD
For AD Ring
UNC_H_SBO0_CREDIT_OCCUPANCY.BL
For BL Ring
UNC_H_SBO1_CREDITS_ACQUIRED.AD
For AD Ring
UNC_H_SBO1_CREDITS_ACQUIRED.BL
For BL Ring
UNC_H_SBO1_CREDIT_OCCUPANCY.AD
For AD Ring
UNC_H_SBO1_CREDIT_OCCUPANCY.BL
For BL Ring
UNC_H_SNOOPS_RSP_AFTER_DATA.LOCAL
Local Requests
UNC_H_SNOOPS_RSP_AFTER_DATA.REMOTE
Remote Requests
UNC_H_SNOOP_CYCLES_NE.ALL
All Requests
UNC_H_SNOOP_CYCLES_NE.LOCAL
Local Requests
UNC_H_SNOOP_CYCLES_NE.REMOTE
Remote Requests
UNC_H_SNOOP_OCCUPANCY.LOCAL
Local Requests
UNC_H_SNOOP_OCCUPANCY.REMOTE
Remote Requests
UNC_H_SNOOP_RESP.RSPCNFLCT
RSPCNFLCT*
UNC_H_SNOOP_RESP.RSPI
RspI
UNC_H_SNOOP_RESP.RSPIFWD
RspIFwd
UNC_H_SNOOP_RESP.RSPS
RspS
UNC_H_SNOOP_RESP.RSPSFWD
RspSFwd
UNC_H_SNOOP_RESP.RSP_FWD_WB
Rsp*Fwd*WB
UNC_H_SNOOP_RESP.RSP_WB
Rsp*WB
UNC_H_SNP_RESP_RECV_LOCAL.OTHER
Other
UNC_H_SNP_RESP_RECV_LOCAL.RSPCNFLCT
RspCnflct
UNC_H_SNP_RESP_RECV_LOCAL.RSPI
RspI
UNC_H_SNP_RESP_RECV_LOCAL.RSPIFWD
RspIFwd
UNC_H_SNP_RESP_RECV_LOCAL.RSPS
RspS
UNC_H_SNP_RESP_RECV_LOCAL.RSPSFWD
RspSFwd
UNC_H_SNP_RESP_RECV_LOCAL.RSPxFWDxWB
Rsp*FWD*WB
UNC_H_SNP_RESP_RECV_LOCAL.RSPxWB
Rsp*WB
UNC_H_STALL_NO_SBO_CREDIT.SBO0_AD
For SBo0, AD Ring
UNC_H_STALL_NO_SBO_CREDIT.SBO0_BL
For SBo0, BL Ring
UNC_H_STALL_NO_SBO_CREDIT.SBO1_AD
For SBo1, AD Ring
UNC_H_STALL_NO_SBO_CREDIT.SBO1_BL
For SBo1, BL Ring
UNC_H_TAD_REQUESTS_G0.REGION0
TAD Region 0
UNC_H_TAD_REQUESTS_G0.REGION1
TAD Region 1
UNC_H_TAD_REQUESTS_G0.REGION2
TAD Region 2
UNC_H_TAD_REQUESTS_G0.REGION3
TAD Region 3
UNC_H_TAD_REQUESTS_G0.REGION4
TAD Region 4
UNC_H_TAD_REQUESTS_G0.REGION5
TAD Region 5
UNC_H_TAD_REQUESTS_G0.REGION6
TAD Region 6
UNC_H_TAD_REQUESTS_G0.REGION7
TAD Region 7
UNC_H_TAD_REQUESTS_G1.REGION10
TAD Region 10
UNC_H_TAD_REQUESTS_G1.REGION11
TAD Region 11
UNC_H_TAD_REQUESTS_G1.REGION8
TAD Region 8
UNC_H_TAD_REQUESTS_G1.REGION9
TAD Region 9
UNC_H_TRACKER_CYCLES_FULL.ALL
Cycles Completely Used
UNC_H_TRACKER_CYCLES_FULL.GP
Cycles GP Completely Used
UNC_H_TRACKER_CYCLES_NE.ALL
All Requests
UNC_H_TRACKER_CYCLES_NE.LOCAL
Local Requests
UNC_H_TRACKER_CYCLES_NE.REMOTE
Remote Requests
UNC_H_TRACKER_OCCUPANCY.INVITOE_LOCAL
Local InvItoE Requests
UNC_H_TRACKER_OCCUPANCY.INVITOE_REMOTE
Remote InvItoE Requests
UNC_H_TRACKER_OCCUPANCY.READS_LOCAL
Local Read Requests
UNC_H_TRACKER_OCCUPANCY.READS_REMOTE
Remote Read Requests
UNC_H_TRACKER_OCCUPANCY.WRITES_LOCAL
Local Write Requests
UNC_H_TRACKER_OCCUPANCY.WRITES_REMOTE
Remote Write Requests
UNC_H_TRACKER_PENDING_OCCUPANCY.LOCAL
Local Requests
UNC_H_TRACKER_PENDING_OCCUPANCY.REMOTE
Remote Requests
UNC_H_TxR_AD.HOM
Non-data Responses
UNC_H_TxR_AD_CYCLES_FULL.ALL
All
UNC_H_TxR_AD_CYCLES_FULL.SCHED0
Scheduler 0
UNC_H_TxR_AD_CYCLES_FULL.SCHED1
Scheduler 1
UNC_H_TxR_AD_CYCLES_NE.ALL
All
UNC_H_TxR_AD_CYCLES_NE.SCHED0
Scheduler 0
UNC_H_TxR_AD_CYCLES_NE.SCHED1
Scheduler 1
UNC_H_TxR_AD_INSERTS.ALL
All
UNC_H_TxR_AD_INSERTS.SCHED0
Scheduler 0
UNC_H_TxR_AD_INSERTS.SCHED1
Scheduler 1
UNC_H_TxR_AK_CYCLES_FULL.ALL
All
UNC_H_TxR_AK_CYCLES_FULL.SCHED0
Scheduler 0
UNC_H_TxR_AK_CYCLES_FULL.SCHED1
Scheduler 1
UNC_H_TxR_AK_CYCLES_NE.ALL
All
UNC_H_TxR_AK_CYCLES_NE.SCHED0
Scheduler 0
UNC_H_TxR_AK_CYCLES_NE.SCHED1
Scheduler 1
UNC_H_TxR_AK_INSERTS.ALL
All
UNC_H_TxR_AK_INSERTS.SCHED0
Scheduler 0
UNC_H_TxR_AK_INSERTS.SCHED1
Scheduler 1
UNC_H_TxR_BL.DRS_CACHE
Data to Cache
UNC_H_TxR_BL.DRS_CORE
Data to Core
UNC_H_TxR_BL.DRS_QPI
Data to QPI
UNC_H_TxR_BL_CYCLES_FULL.ALL
All
UNC_H_TxR_BL_CYCLES_FULL.SCHED0
Scheduler 0
UNC_H_TxR_BL_CYCLES_FULL.SCHED1
Scheduler 1
UNC_H_TxR_BL_CYCLES_NE.ALL
All
UNC_H_TxR_BL_CYCLES_NE.SCHED0
Scheduler 0
UNC_H_TxR_BL_CYCLES_NE.SCHED1
Scheduler 1
UNC_H_TxR_BL_INSERTS.ALL
All
UNC_H_TxR_BL_INSERTS.SCHED0
Scheduler 0
UNC_H_TxR_BL_INSERTS.SCHED1
Scheduler 1
UNC_H_TxR_STARVED.AK
For AK Ring
UNC_H_TxR_STARVED.BL
For BL Ring
UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN0
Channel 0
UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN1
Channel 1
UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN2
Channel 2
UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN3
Channel 3
UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN0
Channel 0
UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN1
Channel 1
UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN2
Channel 2
UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN3
Channel 3
UNC_I_CACHE_TOTAL_OCCUPANCY.ANY
Any Source
UNC_I_CACHE_TOTAL_OCCUPANCY.SOURCE
Select Source
UNC_I_CLOCKTICKS
Clocks in the IRP
UNC_I_COHERENT_OPS.CLFLUSH
CLFlush
UNC_I_COHERENT_OPS.CRD
CRd
UNC_I_COHERENT_OPS.DRD
DRd
UNC_I_COHERENT_OPS.PCIDCAHINT
PCIDCAHin5t
UNC_I_COHERENT_OPS.PCIRDCUR
PCIRdCur
UNC_I_COHERENT_OPS.PCITOM
PCIItoM
UNC_I_COHERENT_OPS.RFO
RFO
UNC_I_COHERENT_OPS.WBMTOI
WbMtoI
UNC_I_MISC0.2ND_ATOMIC_INSERT
Cache Inserts of Atomic Transactions as Secondary
UNC_I_MISC0.2ND_RD_INSERT
Cache Inserts of Read Transactions as Secondary
UNC_I_MISC0.2ND_WR_INSERT
Cache Inserts of Write Transactions as Secondary
UNC_I_MISC0.FAST_REJ
Fastpath Rejects
UNC_I_MISC0.FAST_REQ
Fastpath Requests
UNC_I_MISC0.FAST_XFER
Fastpath Transfers From Primary to Secondary
UNC_I_MISC0.PF_ACK_HINT
Prefetch Ack Hints From Primary to Secondary
UNC_I_MISC0.PF_TIMEOUT
Prefetch TimeOut
UNC_I_MISC0.UNKNOWN
Misc Events - Set 0
UNC_I_MISC1.DATA_THROTTLE
Data Throttled
UNC_I_MISC1.LOST_FWD
Misc Events - Set 1
UNC_I_MISC1.SEC_RCVD_INVLD
Received Invalid
UNC_I_MISC1.SEC_RCVD_VLD
Received Valid
UNC_I_MISC1.SLOW_E
Slow Transfer of E Line
UNC_I_MISC1.SLOW_I
Slow Transfer of I Line
UNC_I_MISC1.SLOW_M
Slow Transfer of M Line
UNC_I_MISC1.SLOW_S
Slow Transfer of S Line
UNC_I_RxR_AK_INSERTS
AK Ingress Occupancy
UNC_I_RxR_BL_DRS_CYCLES_FULL
tbd
UNC_I_RxR_BL_DRS_INSERTS
BL Ingress Occupancy - DRS
UNC_I_RxR_BL_DRS_OCCUPANCY
tbd
UNC_I_RxR_BL_NCB_CYCLES_FULL
tbd
UNC_I_RxR_BL_NCB_INSERTS
BL Ingress Occupancy - NCB
UNC_I_RxR_BL_NCB_OCCUPANCY
tbd
UNC_I_RxR_BL_NCS_CYCLES_FULL
tbd
UNC_I_RxR_BL_NCS_INSERTS
BL Ingress Occupancy - NCS
UNC_I_RxR_BL_NCS_OCCUPANCY
tbd
UNC_I_SNOOP_RESP.HIT_ES
Hit E or S
UNC_I_SNOOP_RESP.HIT_I
Hit I
UNC_I_SNOOP_RESP.HIT_M
Hit M
UNC_I_SNOOP_RESP.MISS
Miss
UNC_I_SNOOP_RESP.SNPCODE
SnpCode
UNC_I_SNOOP_RESP.SNPDATA
SnpData
UNC_I_SNOOP_RESP.SNPINV
SnpInv
UNC_I_TRANSACTIONS.ATOMIC
Atomic
UNC_I_TRANSACTIONS.ORDERINGQ
Select Source
UNC_I_TRANSACTIONS.OTHER
Other
UNC_I_TRANSACTIONS.RD_PREF
Read Prefetches
UNC_I_TRANSACTIONS.READS
Reads
UNC_I_TRANSACTIONS.WRITES
Writes
UNC_I_TRANSACTIONS.WR_PREF
Write Prefetches
UNC_I_TxR_AD_STALL_CREDIT_CYCLES
No AD Egress Credit Stalls
UNC_I_TxR_BL_STALL_CREDIT_CYCLES
No BL Egress Credit Stalls
UNC_I_TxR_DATA_INSERTS_NCB
Outbound Read Requests
UNC_I_TxR_DATA_INSERTS_NCS
Outbound Read Requests
UNC_I_TxR_REQUEST_OCCUPANCY
Outbound Request Queue Occupancy
UNC_M_ACT_COUNT.BYP
Activate due to Write
UNC_M_ACT_COUNT.RD
Activate due to Read
UNC_M_ACT_COUNT.WR
Activate due to Write
UNC_M_BYP_CMDS.ACT
ACT command issued by 2 cycle bypass
UNC_M_BYP_CMDS.CAS
CAS command issued by 2 cycle bypass
UNC_M_BYP_CMDS.PRE
PRE command issued by 2 cycle bypass
UNC_M_CAS_COUNT.ALL
All DRAM WR_CAS (w/ and w/out auto-pre)
UNC_M_CAS_COUNT.RD
All DRAM Reads (RD_CAS + Underfills)
UNC_M_CAS_COUNT.RD_REG
All DRAM RD_CAS (w/ and w/out auto-pre)
UNC_M_CAS_COUNT.RD_RMM
Read CAS issued in RMM
UNC_M_CAS_COUNT.RD_UNDERFILL
Underfill Read Issued
UNC_M_CAS_COUNT.RD_WMM
Read CAS issued in WMM
UNC_M_CAS_COUNT.WR
All DRAM WR_CAS (both Modes)
UNC_M_CAS_COUNT.WR_RMM
DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mode
UNC_M_CAS_COUNT.WR_WMM
DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode
UNC_M_CLOCKTICKS
DRAM Clockticks
UNC_M_DCLOCKTICKS
DRAM Clockticks
UNC_M_DRAM_PRE_ALL
DRAM Precharge All Commands
UNC_M_DRAM_REFRESH.HIGH
Number of DRAM Refreshes Issued
UNC_M_DRAM_REFRESH.PANIC
Number of DRAM Refreshes Issued
UNC_M_ECC_CORRECTABLE_ERRORS
ECC Correctable Errors
UNC_M_MAJOR_MODES.ISOCH
Isoch Major Mode
UNC_M_MAJOR_MODES.PARTIAL
Partial Major Mode
UNC_M_MAJOR_MODES.READ
Read Major Mode
UNC_M_MAJOR_MODES.WRITE
Write Major Mode
UNC_M_POWER_CHANNEL_DLLOFF
Channel DLLOFF Cycles
UNC_M_POWER_CHANNEL_PPD
Channel PPD Cycles
UNC_M_POWER_CKE_CYCLES.RANK0
DIMM ID
UNC_M_POWER_CKE_CYCLES.RANK1
DIMM ID
UNC_M_POWER_CKE_CYCLES.RANK2
DIMM ID
UNC_M_POWER_CKE_CYCLES.RANK3
DIMM ID
UNC_M_POWER_CKE_CYCLES.RANK4
DIMM ID
UNC_M_POWER_CKE_CYCLES.RANK5
DIMM ID
UNC_M_POWER_CKE_CYCLES.RANK6
DIMM ID
UNC_M_POWER_CKE_CYCLES.RANK7
DIMM ID
UNC_M_POWER_CRITICAL_THROTTLE_CYCLES
Critical Throttle Cycles
UNC_M_POWER_PCU_THROTTLING
tbd
UNC_M_POWER_SELF_REFRESH
Clock-Enabled Self-Refresh
UNC_M_POWER_THROTTLE_CYCLES.RANK0
DIMM ID
UNC_M_POWER_THROTTLE_CYCLES.RANK1
DIMM ID
UNC_M_POWER_THROTTLE_CYCLES.RANK2
DIMM ID
UNC_M_POWER_THROTTLE_CYCLES.RANK3
DIMM ID
UNC_M_POWER_THROTTLE_CYCLES.RANK4
DIMM ID
UNC_M_POWER_THROTTLE_CYCLES.RANK5
DIMM ID
UNC_M_POWER_THROTTLE_CYCLES.RANK6
DIMM ID
UNC_M_POWER_THROTTLE_CYCLES.RANK7
DIMM ID
UNC_M_PREEMPTION.RD_PREEMPT_RD
Read over Read Preemption
UNC_M_PREEMPTION.RD_PREEMPT_WR
Read over Write Preemption
UNC_M_PRE_COUNT.BYP
Precharge due to bypass
UNC_M_PRE_COUNT.PAGE_CLOSE
Precharge due to timer expiration
UNC_M_PRE_COUNT.PAGE_MISS
Precharges due to page miss
UNC_M_PRE_COUNT.RD
Precharge due to read
UNC_M_PRE_COUNT.WR
Precharge due to write
UNC_M_RD_CAS_PRIO.HIGH
Read CAS issued with HIGH priority
UNC_M_RD_CAS_PRIO.LOW
Read CAS issued with LOW priority
UNC_M_RD_CAS_PRIO.MED
Read CAS issued with MEDIUM priority
UNC_M_RD_CAS_PRIO.PANIC
Read CAS issued with PANIC NON ISOCH priority (starved)
UNC_M_RD_CAS_RANK0.ALLBANKS
All Banks
UNC_M_RD_CAS_RANK0.BANK0
Bank 0
UNC_M_RD_CAS_RANK0.BANK1
Bank 1
UNC_M_RD_CAS_RANK0.BANK10
Bank 10
UNC_M_RD_CAS_RANK0.BANK11
Bank 11
UNC_M_RD_CAS_RANK0.BANK12
Bank 12
UNC_M_RD_CAS_RANK0.BANK13
Bank 13
UNC_M_RD_CAS_RANK0.BANK14
Bank 14
UNC_M_RD_CAS_RANK0.BANK15
Bank 15
UNC_M_RD_CAS_RANK0.BANK2
Bank 2
UNC_M_RD_CAS_RANK0.BANK3
Bank 3
UNC_M_RD_CAS_RANK0.BANK4
Bank 4
UNC_M_RD_CAS_RANK0.BANK5
Bank 5
UNC_M_RD_CAS_RANK0.BANK6
Bank 6
UNC_M_RD_CAS_RANK0.BANK7
Bank 7
UNC_M_RD_CAS_RANK0.BANK8
Bank 8
UNC_M_RD_CAS_RANK0.BANK9
Bank 9
UNC_M_RD_CAS_RANK0.BANKG0
Bank Group 0 (Banks 0-3)
UNC_M_RD_CAS_RANK0.BANKG1
Bank Group 1 (Banks 4-7)
UNC_M_RD_CAS_RANK0.BANKG2
Bank Group 2 (Banks 8-11)
UNC_M_RD_CAS_RANK0.BANKG3
Bank Group 3 (Banks 12-15)
UNC_M_RD_CAS_RANK1.ALLBANKS
All Banks
UNC_M_RD_CAS_RANK1.BANK0
Bank 0
UNC_M_RD_CAS_RANK1.BANK1
Bank 1
UNC_M_RD_CAS_RANK1.BANK10
Bank 10
UNC_M_RD_CAS_RANK1.BANK11
Bank 11
UNC_M_RD_CAS_RANK1.BANK12
Bank 12
UNC_M_RD_CAS_RANK1.BANK13
Bank 13
UNC_M_RD_CAS_RANK1.BANK14
Bank 14
UNC_M_RD_CAS_RANK1.BANK15
Bank 15
UNC_M_RD_CAS_RANK1.BANK2
Bank 2
UNC_M_RD_CAS_RANK1.BANK3
Bank 3
UNC_M_RD_CAS_RANK1.BANK4
Bank 4
UNC_M_RD_CAS_RANK1.BANK5
Bank 5
UNC_M_RD_CAS_RANK1.BANK6
Bank 6
UNC_M_RD_CAS_RANK1.BANK7
Bank 7
UNC_M_RD_CAS_RANK1.BANK8
Bank 8
UNC_M_RD_CAS_RANK1.BANK9
Bank 9
UNC_M_RD_CAS_RANK1.BANKG0
Bank Group 0 (Banks 0-3)
UNC_M_RD_CAS_RANK1.BANKG1
Bank Group 1 (Banks 4-7)
UNC_M_RD_CAS_RANK1.BANKG2
Bank Group 2 (Banks 8-11)
UNC_M_RD_CAS_RANK1.BANKG3
Bank Group 3 (Banks 12-15)
UNC_M_RD_CAS_RANK2.BANK0
Bank 0
UNC_M_RD_CAS_RANK4.ALLBANKS
All Banks
UNC_M_RD_CAS_RANK4.BANK0
Bank 0
UNC_M_RD_CAS_RANK4.BANK1
Bank 1
UNC_M_RD_CAS_RANK4.BANK10
Bank 10
UNC_M_RD_CAS_RANK4.BANK11
Bank 11
UNC_M_RD_CAS_RANK4.BANK12
Bank 12
UNC_M_RD_CAS_RANK4.BANK13
Bank 13
UNC_M_RD_CAS_RANK4.BANK14
Bank 14
UNC_M_RD_CAS_RANK4.BANK15
Bank 15
UNC_M_RD_CAS_RANK4.BANK2
Bank 2
UNC_M_RD_CAS_RANK4.BANK3
Bank 3
UNC_M_RD_CAS_RANK4.BANK4
Bank 4
UNC_M_RD_CAS_RANK4.BANK5
Bank 5
UNC_M_RD_CAS_RANK4.BANK6
Bank 6
UNC_M_RD_CAS_RANK4.BANK7
Bank 7
UNC_M_RD_CAS_RANK4.BANK8
Bank 8
UNC_M_RD_CAS_RANK4.BANK9
Bank 9
UNC_M_RD_CAS_RANK4.BANKG0
Bank Group 0 (Banks 0-3)
UNC_M_RD_CAS_RANK4.BANKG1
Bank Group 1 (Banks 4-7)
UNC_M_RD_CAS_RANK4.BANKG2
Bank Group 2 (Banks 8-11)
UNC_M_RD_CAS_RANK4.BANKG3
Bank Group 3 (Banks 12-15)
UNC_M_RD_CAS_RANK5.ALLBANKS
All Banks
UNC_M_RD_CAS_RANK5.BANK0
Bank 0
UNC_M_RD_CAS_RANK5.BANK1
Bank 1
UNC_M_RD_CAS_RANK5.BANK10
Bank 10
UNC_M_RD_CAS_RANK5.BANK11
Bank 11
UNC_M_RD_CAS_RANK5.BANK12
Bank 12
UNC_M_RD_CAS_RANK5.BANK13
Bank 13
UNC_M_RD_CAS_RANK5.BANK14
Bank 14
UNC_M_RD_CAS_RANK5.BANK15
Bank 15
UNC_M_RD_CAS_RANK5.BANK2
Bank 2
UNC_M_RD_CAS_RANK5.BANK3
Bank 3
UNC_M_RD_CAS_RANK5.BANK4
Bank 4
UNC_M_RD_CAS_RANK5.BANK5
Bank 5
UNC_M_RD_CAS_RANK5.BANK6
Bank 6
UNC_M_RD_CAS_RANK5.BANK7
Bank 7
UNC_M_RD_CAS_RANK5.BANK8
Bank 8
UNC_M_RD_CAS_RANK5.BANK9
Bank 9
UNC_M_RD_CAS_RANK5.BANKG0
Bank Group 0 (Banks 0-3)
UNC_M_RD_CAS_RANK5.BANKG1
Bank Group 1 (Banks 4-7)
UNC_M_RD_CAS_RANK5.BANKG2
Bank Group 2 (Banks 8-11)
UNC_M_RD_CAS_RANK5.BANKG3
Bank Group 3 (Banks 12-15)
UNC_M_RD_CAS_RANK6.ALLBANKS
All Banks
UNC_M_RD_CAS_RANK6.BANK0
Bank 0
UNC_M_RD_CAS_RANK6.BANK1
Bank 1
UNC_M_RD_CAS_RANK6.BANK10
Bank 10
UNC_M_RD_CAS_RANK6.BANK11
Bank 11
UNC_M_RD_CAS_RANK6.BANK12
Bank 12
UNC_M_RD_CAS_RANK6.BANK13
Bank 13
UNC_M_RD_CAS_RANK6.BANK14
Bank 14
UNC_M_RD_CAS_RANK6.BANK15
Bank 15
UNC_M_RD_CAS_RANK6.BANK2
Bank 2
UNC_M_RD_CAS_RANK6.BANK3
Bank 3
UNC_M_RD_CAS_RANK6.BANK4
Bank 4
UNC_M_RD_CAS_RANK6.BANK5
Bank 5
UNC_M_RD_CAS_RANK6.BANK6
Bank 6
UNC_M_RD_CAS_RANK6.BANK7
Bank 7
UNC_M_RD_CAS_RANK6.BANK8
Bank 8
UNC_M_RD_CAS_RANK6.BANK9
Bank 9
UNC_M_RD_CAS_RANK6.BANKG0
Bank Group 0 (Banks 0-3)
UNC_M_RD_CAS_RANK6.BANKG1
Bank Group 1 (Banks 4-7)
UNC_M_RD_CAS_RANK6.BANKG2
Bank Group 2 (Banks 8-11)
UNC_M_RD_CAS_RANK6.BANKG3
Bank Group 3 (Banks 12-15)
UNC_M_RD_CAS_RANK7.ALLBANKS
All Banks
UNC_M_RD_CAS_RANK7.BANK0
Bank 0
UNC_M_RD_CAS_RANK7.BANK1
Bank 1
UNC_M_RD_CAS_RANK7.BANK10
Bank 10
UNC_M_RD_CAS_RANK7.BANK11
Bank 11
UNC_M_RD_CAS_RANK7.BANK12
Bank 12
UNC_M_RD_CAS_RANK7.BANK13
Bank 13
UNC_M_RD_CAS_RANK7.BANK14
Bank 14
UNC_M_RD_CAS_RANK7.BANK15
Bank 15
UNC_M_RD_CAS_RANK7.BANK2
Bank 2
UNC_M_RD_CAS_RANK7.BANK3
Bank 3
UNC_M_RD_CAS_RANK7.BANK4
Bank 4
UNC_M_RD_CAS_RANK7.BANK5
Bank 5
UNC_M_RD_CAS_RANK7.BANK6
Bank 6
UNC_M_RD_CAS_RANK7.BANK7
Bank 7
UNC_M_RD_CAS_RANK7.BANK8
Bank 8
UNC_M_RD_CAS_RANK7.BANK9
Bank 9
UNC_M_RD_CAS_RANK7.BANKG0
Bank Group 0 (Banks 0-3)
UNC_M_RD_CAS_RANK7.BANKG1
Bank Group 1 (Banks 4-7)
UNC_M_RD_CAS_RANK7.BANKG2
Bank Group 2 (Banks 8-11)
UNC_M_RD_CAS_RANK7.BANKG3
Bank Group 3 (Banks 12-15)
UNC_M_RPQ_CYCLES_NE
Read Pending Queue Not Empty
UNC_M_RPQ_INSERTS
Read Pending Queue Allocations
UNC_M_VMSE_MXB_WR_OCCUPANCY
VMSE MXB write buffer occupancy
UNC_M_VMSE_WR_PUSH.RMM
VMSE write PUSH issued in RMM
UNC_M_VMSE_WR_PUSH.WMM
VMSE write PUSH issued in WMM
UNC_M_WMM_TO_RMM.LOW_THRESH
Transition from WMM to RMM because of starve counter
UNC_M_WMM_TO_RMM.STARVE
Transition from WMM to RMM because of low threshold
UNC_M_WMM_TO_RMM.VMSE_RETRY
Transition from WMM to RMM because of low threshold
UNC_M_WPQ_CYCLES_FULL
Write Pending Queue Full Cycles
UNC_M_WPQ_CYCLES_NE
Write Pending Queue Not Empty
UNC_M_WPQ_READ_HIT
Write Pending Queue CAM Match
UNC_M_WPQ_WRITE_HIT
Write Pending Queue CAM Match
UNC_M_WRONG_MM
Not getting the requested Major Mode
UNC_M_WR_CAS_RANK0.ALLBANKS
All Banks
UNC_M_WR_CAS_RANK0.BANK0
Bank 0
UNC_M_WR_CAS_RANK0.BANK1
Bank 1
UNC_M_WR_CAS_RANK0.BANK10
Bank 10
UNC_M_WR_CAS_RANK0.BANK11
Bank 11
UNC_M_WR_CAS_RANK0.BANK12
Bank 12
UNC_M_WR_CAS_RANK0.BANK13
Bank 13
UNC_M_WR_CAS_RANK0.BANK14
Bank 14
UNC_M_WR_CAS_RANK0.BANK15
Bank 15
UNC_M_WR_CAS_RANK0.BANK2
Bank 2
UNC_M_WR_CAS_RANK0.BANK3
Bank 3
UNC_M_WR_CAS_RANK0.BANK4
Bank 4
UNC_M_WR_CAS_RANK0.BANK5
Bank 5
UNC_M_WR_CAS_RANK0.BANK6
Bank 6
UNC_M_WR_CAS_RANK0.BANK7
Bank 7
UNC_M_WR_CAS_RANK0.BANK8
Bank 8
UNC_M_WR_CAS_RANK0.BANK9
Bank 9
UNC_M_WR_CAS_RANK0.BANKG0
Bank Group 0 (Banks 0-3)
UNC_M_WR_CAS_RANK0.BANKG1
Bank Group 1 (Banks 4-7)
UNC_M_WR_CAS_RANK0.BANKG2
Bank Group 2 (Banks 8-11)
UNC_M_WR_CAS_RANK0.BANKG3
Bank Group 3 (Banks 12-15)
UNC_M_WR_CAS_RANK1.ALLBANKS
All Banks
UNC_M_WR_CAS_RANK1.BANK0
Bank 0
UNC_M_WR_CAS_RANK1.BANK1
Bank 1
UNC_M_WR_CAS_RANK1.BANK10
Bank 10
UNC_M_WR_CAS_RANK1.BANK11
Bank 11
UNC_M_WR_CAS_RANK1.BANK12
Bank 12
UNC_M_WR_CAS_RANK1.BANK13
Bank 13
UNC_M_WR_CAS_RANK1.BANK14
Bank 14
UNC_M_WR_CAS_RANK1.BANK15
Bank 15
UNC_M_WR_CAS_RANK1.BANK2
Bank 2
UNC_M_WR_CAS_RANK1.BANK3
Bank 3
UNC_M_WR_CAS_RANK1.BANK4
Bank 4
UNC_M_WR_CAS_RANK1.BANK5
Bank 5
UNC_M_WR_CAS_RANK1.BANK6
Bank 6
UNC_M_WR_CAS_RANK1.BANK7
Bank 7
UNC_M_WR_CAS_RANK1.BANK8
Bank 8
UNC_M_WR_CAS_RANK1.BANK9
Bank 9
UNC_M_WR_CAS_RANK1.BANKG0
Bank Group 0 (Banks 0-3)
UNC_M_WR_CAS_RANK1.BANKG1
Bank Group 1 (Banks 4-7)
UNC_M_WR_CAS_RANK1.BANKG2
Bank Group 2 (Banks 8-11)
UNC_M_WR_CAS_RANK1.BANKG3
Bank Group 3 (Banks 12-15)
UNC_M_WR_CAS_RANK4.ALLBANKS
All Banks
UNC_M_WR_CAS_RANK4.BANK0
Bank 0
UNC_M_WR_CAS_RANK4.BANK1
Bank 1
UNC_M_WR_CAS_RANK4.BANK10
Bank 10
UNC_M_WR_CAS_RANK4.BANK11
Bank 11
UNC_M_WR_CAS_RANK4.BANK12
Bank 12
UNC_M_WR_CAS_RANK4.BANK13
Bank 13
UNC_M_WR_CAS_RANK4.BANK14
Bank 14
UNC_M_WR_CAS_RANK4.BANK15
Bank 15
UNC_M_WR_CAS_RANK4.BANK2
Bank 2
UNC_M_WR_CAS_RANK4.BANK3
Bank 3
UNC_M_WR_CAS_RANK4.BANK4
Bank 4
UNC_M_WR_CAS_RANK4.BANK5
Bank 5
UNC_M_WR_CAS_RANK4.BANK6
Bank 6
UNC_M_WR_CAS_RANK4.BANK7
Bank 7
UNC_M_WR_CAS_RANK4.BANK8
Bank 8
UNC_M_WR_CAS_RANK4.BANK9
Bank 9
UNC_M_WR_CAS_RANK4.BANKG0
Bank Group 0 (Banks 0-3)
UNC_M_WR_CAS_RANK4.BANKG1
Bank Group 1 (Banks 4-7)
UNC_M_WR_CAS_RANK4.BANKG2
Bank Group 2 (Banks 8-11)
UNC_M_WR_CAS_RANK4.BANKG3
Bank Group 3 (Banks 12-15)
UNC_M_WR_CAS_RANK5.ALLBANKS
All Banks
UNC_M_WR_CAS_RANK5.BANK0
Bank 0
UNC_M_WR_CAS_RANK5.BANK1
Bank 1
UNC_M_WR_CAS_RANK5.BANK10
Bank 10
UNC_M_WR_CAS_RANK5.BANK11
Bank 11
UNC_M_WR_CAS_RANK5.BANK12
Bank 12
UNC_M_WR_CAS_RANK5.BANK13
Bank 13
UNC_M_WR_CAS_RANK5.BANK14
Bank 14
UNC_M_WR_CAS_RANK5.BANK15
Bank 15
UNC_M_WR_CAS_RANK5.BANK2
Bank 2
UNC_M_WR_CAS_RANK5.BANK3
Bank 3
UNC_M_WR_CAS_RANK5.BANK4
Bank 4
UNC_M_WR_CAS_RANK5.BANK5
Bank 5
UNC_M_WR_CAS_RANK5.BANK6
Bank 6
UNC_M_WR_CAS_RANK5.BANK7
Bank 7
UNC_M_WR_CAS_RANK5.BANK8
Bank 8
UNC_M_WR_CAS_RANK5.BANK9
Bank 9
UNC_M_WR_CAS_RANK5.BANKG0
Bank Group 0 (Banks 0-3)
UNC_M_WR_CAS_RANK5.BANKG1
Bank Group 1 (Banks 4-7)
UNC_M_WR_CAS_RANK5.BANKG2
Bank Group 2 (Banks 8-11)
UNC_M_WR_CAS_RANK5.BANKG3
Bank Group 3 (Banks 12-15)
UNC_M_WR_CAS_RANK6.ALLBANKS
All Banks
UNC_M_WR_CAS_RANK6.BANK0
Bank 0
UNC_M_WR_CAS_RANK6.BANK1
Bank 1
UNC_M_WR_CAS_RANK6.BANK10
Bank 10
UNC_M_WR_CAS_RANK6.BANK11
Bank 11
UNC_M_WR_CAS_RANK6.BANK12
Bank 12
UNC_M_WR_CAS_RANK6.BANK13
Bank 13
UNC_M_WR_CAS_RANK6.BANK14
Bank 14
UNC_M_WR_CAS_RANK6.BANK15
Bank 15
UNC_M_WR_CAS_RANK6.BANK2
Bank 2
UNC_M_WR_CAS_RANK6.BANK3
Bank 3
UNC_M_WR_CAS_RANK6.BANK4
Bank 4
UNC_M_WR_CAS_RANK6.BANK5
Bank 5
UNC_M_WR_CAS_RANK6.BANK6
Bank 6
UNC_M_WR_CAS_RANK6.BANK7
Bank 7
UNC_M_WR_CAS_RANK6.BANK8
Bank 8
UNC_M_WR_CAS_RANK6.BANK9
Bank 9
UNC_M_WR_CAS_RANK6.BANKG0
Bank Group 0 (Banks 0-3)
UNC_M_WR_CAS_RANK6.BANKG1
Bank Group 1 (Banks 4-7)
UNC_M_WR_CAS_RANK6.BANKG2
Bank Group 2 (Banks 8-11)
UNC_M_WR_CAS_RANK6.BANKG3
Bank Group 3 (Banks 12-15)
UNC_M_WR_CAS_RANK7.ALLBANKS
All Banks
UNC_M_WR_CAS_RANK7.BANK0
Bank 0
UNC_M_WR_CAS_RANK7.BANK1
Bank 1
UNC_M_WR_CAS_RANK7.BANK10
Bank 10
UNC_M_WR_CAS_RANK7.BANK11
Bank 11
UNC_M_WR_CAS_RANK7.BANK12
Bank 12
UNC_M_WR_CAS_RANK7.BANK13
Bank 13
UNC_M_WR_CAS_RANK7.BANK14
Bank 14
UNC_M_WR_CAS_RANK7.BANK15
Bank 15
UNC_M_WR_CAS_RANK7.BANK2
Bank 2
UNC_M_WR_CAS_RANK7.BANK3
Bank 3
UNC_M_WR_CAS_RANK7.BANK4
Bank 4
UNC_M_WR_CAS_RANK7.BANK5
Bank 5
UNC_M_WR_CAS_RANK7.BANK6
Bank 6
UNC_M_WR_CAS_RANK7.BANK7
Bank 7
UNC_M_WR_CAS_RANK7.BANK8
Bank 8
UNC_M_WR_CAS_RANK7.BANK9
Bank 9
UNC_M_WR_CAS_RANK7.BANKG0
Bank Group 0 (Banks 0-3)
UNC_M_WR_CAS_RANK7.BANKG1
Bank Group 1 (Banks 4-7)
UNC_M_WR_CAS_RANK7.BANKG2
Bank Group 2 (Banks 8-11)
UNC_M_WR_CAS_RANK7.BANKG3
Bank Group 3 (Banks 12-15)
UNC_P_CLOCKTICKS
pclk Cycles
UNC_P_CORE0_TRANSITION_CYCLES
Core C State Transition Cycles
UNC_P_CORE10_TRANSITION_CYCLES
Core C State Transition Cycles
UNC_P_CORE11_TRANSITION_CYCLES
Core C State Transition Cycles
UNC_P_CORE12_TRANSITION_CYCLES
Core C State Transition Cycles
UNC_P_CORE13_TRANSITION_CYCLES
Core C State Transition Cycles
UNC_P_CORE14_TRANSITION_CYCLES
Core C State Transition Cycles
UNC_P_CORE15_TRANSITION_CYCLES
Core C State Transition Cycles
UNC_P_CORE16_TRANSITION_CYCLES
Core C State Transition Cycles
UNC_P_CORE17_TRANSITION_CYCLES
Core C State Transition Cycles
UNC_P_CORE1_TRANSITION_CYCLES
Core C State Transition Cycles
UNC_P_CORE2_TRANSITION_CYCLES
Core C State Transition Cycles
UNC_P_CORE3_TRANSITION_CYCLES
Core C State Transition Cycles
UNC_P_CORE4_TRANSITION_CYCLES
Core C State Transition Cycles
UNC_P_CORE5_TRANSITION_CYCLES
Core C State Transition Cycles
UNC_P_CORE6_TRANSITION_CYCLES
Core C State Transition Cycles
UNC_P_CORE7_TRANSITION_CYCLES
Core C State Transition Cycles
UNC_P_CORE8_TRANSITION_CYCLES
Core C State Transition Cycles
UNC_P_CORE9_TRANSITION_CYCLES
Core C State Transition Cycles
UNC_P_DEMOTIONS_CORE0
Core C State Demotions
UNC_P_DEMOTIONS_CORE1
Core C State Demotions
UNC_P_DEMOTIONS_CORE10
Core C State Demotions
UNC_P_DEMOTIONS_CORE11
Core C State Demotions
UNC_P_DEMOTIONS_CORE12
Core C State Demotions
UNC_P_DEMOTIONS_CORE13
Core C State Demotions
UNC_P_DEMOTIONS_CORE14
Core C State Demotions
UNC_P_DEMOTIONS_CORE15
Core C State Demotions
UNC_P_DEMOTIONS_CORE16
Core C State Demotions
UNC_P_DEMOTIONS_CORE17
Core C State Demotions
UNC_P_DEMOTIONS_CORE2
Core C State Demotions
UNC_P_DEMOTIONS_CORE3
Core C State Demotions
UNC_P_DEMOTIONS_CORE4
Core C State Demotions
UNC_P_DEMOTIONS_CORE5
Core C State Demotions
UNC_P_DEMOTIONS_CORE6
Core C State Demotions
UNC_P_DEMOTIONS_CORE7
Core C State Demotions
UNC_P_DEMOTIONS_CORE8
Core C State Demotions
UNC_P_DEMOTIONS_CORE9
Core C State Demotions
UNC_P_FREQ_BAND0_CYCLES
Frequency Residency
UNC_P_FREQ_BAND1_CYCLES
Frequency Residency
UNC_P_FREQ_BAND2_CYCLES
Frequency Residency
UNC_P_FREQ_BAND3_CYCLES
Frequency Residency
UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES
Thermal Strongest Upper Limit Cycles
UNC_P_FREQ_MAX_OS_CYCLES
OS Strongest Upper Limit Cycles
UNC_P_FREQ_MAX_POWER_CYCLES
Power Strongest Upper Limit Cycles
UNC_P_FREQ_MIN_IO_P_CYCLES
IO P Limit Strongest Lower Limit Cycles
UNC_P_FREQ_TRANS_CYCLES
Cycles spent changing Frequency
UNC_P_MEMORY_PHASE_SHEDDING_CYCLES
Memory Phase Shedding Cycles
UNC_P_PKG_RESIDENCY_C0_CYCLES
Package C State Residency - C0
UNC_P_PKG_RESIDENCY_C1E_CYCLES
Package C State Residency - C1E
UNC_P_PKG_RESIDENCY_C2E_CYCLES
Package C State Residency - C2E
UNC_P_PKG_RESIDENCY_C3_CYCLES
Package C State Residency - C3
UNC_P_PKG_RESIDENCY_C6_CYCLES
Package C State Residency - C6
UNC_P_PKG_RESIDENCY_C7_CYCLES
Package C7 State Residency
UNC_P_POWER_STATE_OCCUPANCY.CORES_C0
C0 and C1
UNC_P_POWER_STATE_OCCUPANCY.CORES_C3
C3
UNC_P_POWER_STATE_OCCUPANCY.CORES_C6
C6 and C7
UNC_P_PROCHOT_EXTERNAL_CYCLES
External Prochot
UNC_P_PROCHOT_INTERNAL_CYCLES
Internal Prochot
UNC_P_TOTAL_TRANSITION_CYCLES
Total Core C State Transition Cycles
UNC_P_UFS_TRANSITIONS_NO_CHANGE
tbd
UNC_P_UFS_TRANSITIONS_RING_GV
tbd
UNC_P_VR_HOT_CYCLES
VR Hot
UNC_Q_CLOCKTICKS
Number of qfclks
UNC_Q_CTO_COUNT
Count of CTO Events
UNC_Q_DIRECT2CORE.FAILURE_CREDITS
Spawn Failure - Egress Credits
UNC_Q_DIRECT2CORE.FAILURE_CREDITS_MISS
Spawn Failure - Egress and RBT Miss
UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT
Spawn Failure - Egress and RBT Invalid
UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT_MISS
Spawn Failure - Egress and RBT Miss, Invalid
UNC_Q_DIRECT2CORE.FAILURE_MISS
Spawn Failure - RBT Miss
UNC_Q_DIRECT2CORE.FAILURE_RBT_HIT
Spawn Failure - RBT Invalid
UNC_Q_DIRECT2CORE.FAILURE_RBT_MISS
Spawn Failure - RBT Miss and Invalid
UNC_Q_DIRECT2CORE.SUCCESS_RBT_HIT
Spawn Success
UNC_Q_L1_POWER_CYCLES
Cycles in L1
UNC_Q_RxL0P_POWER_CYCLES
Cycles in L0p
UNC_Q_RxL0_POWER_CYCLES
Cycles in L0
UNC_Q_RxL_BYPASSED
Rx Flit Buffer Bypassed
UNC_Q_RxL_CRC_ERRORS.LINK_INIT
LinkInit
UNC_Q_RxL_CRC_ERRORS.NORMAL_OP
Normal Operations
UNC_Q_RxL_CREDITS_CONSUMED_VN0.DRS
DRS
UNC_Q_RxL_CREDITS_CONSUMED_VN0.HOM
HOM
UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCB
NCB
UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCS
NCS
UNC_Q_RxL_CREDITS_CONSUMED_VN0.NDR
NDR
UNC_Q_RxL_CREDITS_CONSUMED_VN0.SNP
SNP
UNC_Q_RxL_CREDITS_CONSUMED_VN1.DRS
DRS
UNC_Q_RxL_CREDITS_CONSUMED_VN1.HOM
HOM
UNC_Q_RxL_CREDITS_CONSUMED_VN1.NCB
NCB
UNC_Q_RxL_CREDITS_CONSUMED_VN1.NCS
NCS
UNC_Q_RxL_CREDITS_CONSUMED_VN1.NDR
NDR
UNC_Q_RxL_CREDITS_CONSUMED_VN1.SNP
SNP
UNC_Q_RxL_CREDITS_CONSUMED_VNA
VNA Credit Consumed
UNC_Q_RxL_CYCLES_NE
RxQ Cycles Not Empty
UNC_Q_RxL_CYCLES_NE_DRS.VN0
for VN0
UNC_Q_RxL_CYCLES_NE_DRS.VN1
for VN1
UNC_Q_RxL_CYCLES_NE_HOM.VN0
for VN0
UNC_Q_RxL_CYCLES_NE_HOM.VN1
for VN1
UNC_Q_RxL_CYCLES_NE_NCB.VN0
for VN0
UNC_Q_RxL_CYCLES_NE_NCB.VN1
for VN1
UNC_Q_RxL_CYCLES_NE_NCS.VN0
for VN0
UNC_Q_RxL_CYCLES_NE_NCS.VN1
for VN1
UNC_Q_RxL_CYCLES_NE_NDR.VN0
for VN0
UNC_Q_RxL_CYCLES_NE_NDR.VN1
for VN1
UNC_Q_RxL_CYCLES_NE_SNP.VN0
for VN0
UNC_Q_RxL_CYCLES_NE_SNP.VN1
for VN1
UNC_Q_RxL_FLITS_G0.IDLE
Idle and Null Flits
UNC_Q_RxL_FLITS_G1.DRS
DRS Flits (both Header and Data)
UNC_Q_RxL_FLITS_G1.DRS_DATA
DRS Data Flits
UNC_Q_RxL_FLITS_G1.DRS_NONDATA
DRS Header Flits
UNC_Q_RxL_FLITS_G1.HOM
HOM Flits
UNC_Q_RxL_FLITS_G1.HOM_NONREQ
HOM Non-Request Flits
UNC_Q_RxL_FLITS_G1.HOM_REQ
HOM Request Flits
UNC_Q_RxL_FLITS_G1.SNP
SNP Flits
UNC_Q_RxL_FLITS_G2.NCB
Non-Coherent Rx Flits
UNC_Q_RxL_FLITS_G2.NCB_DATA
Non-Coherent data Rx Flits
UNC_Q_RxL_FLITS_G2.NCB_NONDATA
Non-Coherent non-data Rx Flits
UNC_Q_RxL_FLITS_G2.NCS
Non-Coherent standard Rx Flits
UNC_Q_RxL_FLITS_G2.NDR_AD
Non-Data Response Rx Flits - AD
UNC_Q_RxL_FLITS_G2.NDR_AK
Non-Data Response Rx Flits - AK
UNC_Q_RxL_INSERTS
Rx Flit Buffer Allocations
UNC_Q_RxL_INSERTS_DRS.VN0
for VN0
UNC_Q_RxL_INSERTS_DRS.VN1
for VN1
UNC_Q_RxL_INSERTS_HOM.VN0
for VN0
UNC_Q_RxL_INSERTS_HOM.VN1
for VN1
UNC_Q_RxL_INSERTS_NCB.VN0
for VN0
UNC_Q_RxL_INSERTS_NCB.VN1
for VN1
UNC_Q_RxL_INSERTS_NCS.VN0
for VN0
UNC_Q_RxL_INSERTS_NCS.VN1
for VN1
UNC_Q_RxL_INSERTS_NDR.VN0
for VN0
UNC_Q_RxL_INSERTS_NDR.VN1
for VN1
UNC_Q_RxL_INSERTS_SNP.VN0
for VN0
UNC_Q_RxL_INSERTS_SNP.VN1
for VN1
UNC_Q_RxL_OCCUPANCY
RxQ Occupancy - All Packets
UNC_Q_RxL_OCCUPANCY_DRS.VN0
for VN0
UNC_Q_RxL_OCCUPANCY_DRS.VN1
for VN1
UNC_Q_RxL_OCCUPANCY_HOM.VN0
for VN0
UNC_Q_RxL_OCCUPANCY_HOM.VN1
for VN1
UNC_Q_RxL_OCCUPANCY_NCB.VN0
for VN0
UNC_Q_RxL_OCCUPANCY_NCB.VN1
for VN1
UNC_Q_RxL_OCCUPANCY_NCS.VN0
for VN0
UNC_Q_RxL_OCCUPANCY_NCS.VN1
for VN1
UNC_Q_RxL_OCCUPANCY_NDR.VN0
for VN0
UNC_Q_RxL_OCCUPANCY_NDR.VN1
for VN1
UNC_Q_RxL_OCCUPANCY_SNP.VN0
for VN0
UNC_Q_RxL_OCCUPANCY_SNP.VN1
for VN1
UNC_Q_RxL_STALLS_VN0.BGF_DRS
BGF Stall - HOM
UNC_Q_RxL_STALLS_VN0.BGF_HOM
BGF Stall - DRS
UNC_Q_RxL_STALLS_VN0.BGF_NCB
BGF Stall - SNP
UNC_Q_RxL_STALLS_VN0.BGF_NCS
BGF Stall - NDR
UNC_Q_RxL_STALLS_VN0.BGF_NDR
BGF Stall - NCS
UNC_Q_RxL_STALLS_VN0.BGF_SNP
BGF Stall - NCB
UNC_Q_RxL_STALLS_VN0.EGRESS_CREDITS
Egress Credits
UNC_Q_RxL_STALLS_VN0.GV
GV
UNC_Q_RxL_STALLS_VN1.BGF_DRS
BGF Stall - HOM
UNC_Q_RxL_STALLS_VN1.BGF_HOM
BGF Stall - DRS
UNC_Q_RxL_STALLS_VN1.BGF_NCB
BGF Stall - SNP
UNC_Q_RxL_STALLS_VN1.BGF_NCS
BGF Stall - NDR
UNC_Q_RxL_STALLS_VN1.BGF_NDR
BGF Stall - NCS
UNC_Q_RxL_STALLS_VN1.BGF_SNP
BGF Stall - NCB
UNC_Q_TxL0P_POWER_CYCLES
Cycles in L0p
UNC_Q_TxL0_POWER_CYCLES
Cycles in L0
UNC_Q_TxL_BYPASSED
Tx Flit Buffer Bypassed
UNC_Q_TxL_CRC_NO_CREDITS.ALMOST_FULL
LLR is almost full
UNC_Q_TxL_CRC_NO_CREDITS.FULL
LLR is full
UNC_Q_TxL_CYCLES_NE
Tx Flit Buffer Cycles not Empty
UNC_Q_TxL_FLITS_G0.DATA
Data Tx Flits
UNC_Q_TxL_FLITS_G0.NON_DATA
Non-Data protocol Tx Flits
UNC_Q_TxL_FLITS_G1.DRS
DRS Flits (both Header and Data)
UNC_Q_TxL_FLITS_G1.DRS_DATA
DRS Data Flits
UNC_Q_TxL_FLITS_G1.DRS_NONDATA
DRS Header Flits
UNC_Q_TxL_FLITS_G1.HOM
HOM Flits
UNC_Q_TxL_FLITS_G1.HOM_NONREQ
HOM Non-Request Flits
UNC_Q_TxL_FLITS_G1.HOM_REQ
HOM Request Flits
UNC_Q_TxL_FLITS_G1.SNP
SNP Flits
UNC_Q_TxL_FLITS_G2.NCB
Non-Coherent Bypass Tx Flits
UNC_Q_TxL_FLITS_G2.NCB_DATA
Non-Coherent data Tx Flits
UNC_Q_TxL_FLITS_G2.NCB_NONDATA
Non-Coherent non-data Tx Flits
UNC_Q_TxL_FLITS_G2.NCS
Non-Coherent standard Tx Flits
UNC_Q_TxL_FLITS_G2.NDR_AD
Non-Data Response Tx Flits - AD
UNC_Q_TxL_FLITS_G2.NDR_AK
Non-Data Response Tx Flits - AK
UNC_Q_TxL_INSERTS
Tx Flit Buffer Allocations
UNC_Q_TxL_OCCUPANCY
Tx Flit Buffer Occupancy
UNC_Q_TxR_AD_HOM_CREDIT_ACQUIRED.VN0
for VN0
UNC_Q_TxR_AD_HOM_CREDIT_ACQUIRED.VN1
for VN1
UNC_Q_TxR_AD_HOM_CREDIT_OCCUPANCY.VN0
for VN0
UNC_Q_TxR_AD_HOM_CREDIT_OCCUPANCY.VN1
for VN1
UNC_Q_TxR_AD_NDR_CREDIT_ACQUIRED.VN0
for VN0
UNC_Q_TxR_AD_NDR_CREDIT_ACQUIRED.VN1
for VN1
UNC_Q_TxR_AD_NDR_CREDIT_OCCUPANCY.VN0
for VN0
UNC_Q_TxR_AD_NDR_CREDIT_OCCUPANCY.VN1
for VN1
UNC_Q_TxR_AD_SNP_CREDIT_ACQUIRED.VN0
for VN0
UNC_Q_TxR_AD_SNP_CREDIT_ACQUIRED.VN1
for VN1
UNC_Q_TxR_AD_SNP_CREDIT_OCCUPANCY.VN0
for VN0
UNC_Q_TxR_AD_SNP_CREDIT_OCCUPANCY.VN1
for VN1
UNC_Q_TxR_AK_NDR_CREDIT_ACQUIRED
R3QPI Egress Credit Occupancy - AK NDR
UNC_Q_TxR_AK_NDR_CREDIT_OCCUPANCY
R3QPI Egress Credit Occupancy - AK NDR
UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN0
for VN0
UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN1
for VN1
UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN_SHR
for Shared VN
UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN0
for VN0
UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN1
for VN1
UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN_SHR
for Shared VN
UNC_Q_TxR_BL_NCB_CREDIT_ACQUIRED.VN0
for VN0
UNC_Q_TxR_BL_NCB_CREDIT_ACQUIRED.VN1
for VN1
UNC_Q_TxR_BL_NCB_CREDIT_OCCUPANCY.VN0
for VN0
UNC_Q_TxR_BL_NCB_CREDIT_OCCUPANCY.VN1
for VN1
UNC_Q_TxR_BL_NCS_CREDIT_ACQUIRED.VN0
for VN0
UNC_Q_TxR_BL_NCS_CREDIT_ACQUIRED.VN1
for VN1
UNC_Q_TxR_BL_NCS_CREDIT_OCCUPANCY.VN0
for VN0
UNC_Q_TxR_BL_NCS_CREDIT_OCCUPANCY.VN1
for VN1
UNC_Q_VNA_CREDIT_RETURNS
VNA Credits Returned
UNC_Q_VNA_CREDIT_RETURN_OCCUPANCY
VNA Credits Pending Return - Occupancy
UNC_R2_CLOCKTICKS
Number of uclks in domain
UNC_R2_IIO_CREDIT.ISOCH_QPI0
tbd
UNC_R2_IIO_CREDIT.ISOCH_QPI1
tbd
UNC_R2_IIO_CREDIT.PRQ_QPI0
tbd
UNC_R2_IIO_CREDIT.PRQ_QPI1
tbd
UNC_R2_IIO_CREDITS_ACQUIRED.DRS
DRS
UNC_R2_IIO_CREDITS_ACQUIRED.NCB
NCB
UNC_R2_IIO_CREDITS_ACQUIRED.NCS
NCS
UNC_R2_IIO_CREDITS_USED.DRS
DRS
UNC_R2_IIO_CREDITS_USED.NCB
NCB
UNC_R2_IIO_CREDITS_USED.NCS
NCS
UNC_R2_RING_AD_USED.CCW
Counterclockwise
UNC_R2_RING_AD_USED.CCW_EVEN
Counterclockwise and Even
UNC_R2_RING_AD_USED.CCW_ODD
Counterclockwise and Odd
UNC_R2_RING_AD_USED.CW
Clockwise
UNC_R2_RING_AD_USED.CW_EVEN
Clockwise and Even
UNC_R2_RING_AD_USED.CW_ODD
Clockwise and Odd
UNC_R2_RING_AK_BOUNCES.DN
Dn
UNC_R2_RING_AK_BOUNCES.UP
Up
UNC_R2_RING_AK_USED.CCW
Counterclockwise
UNC_R2_RING_AK_USED.CCW_EVEN
Counterclockwise and Even
UNC_R2_RING_AK_USED.CCW_ODD
Counterclockwise and Odd
UNC_R2_RING_AK_USED.CW
Clockwise
UNC_R2_RING_AK_USED.CW_EVEN
Clockwise and Even
UNC_R2_RING_AK_USED.CW_ODD
Clockwise and Odd
UNC_R2_RING_BL_USED.CCW
Counterclockwise
UNC_R2_RING_BL_USED.CCW_EVEN
Counterclockwise and Even
UNC_R2_RING_BL_USED.CCW_ODD
Counterclockwise and Odd
UNC_R2_RING_BL_USED.CW
Clockwise
UNC_R2_RING_BL_USED.CW_EVEN
Clockwise and Even
UNC_R2_RING_BL_USED.CW_ODD
Clockwise and Odd
UNC_R2_RING_IV_USED.ANY
Any
UNC_R2_RING_IV_USED.CCW
Counterclockwise
UNC_R2_RING_IV_USED.CW
Clockwise
UNC_R2_RxR_CYCLES_NE.NCB
NCB
UNC_R2_RxR_CYCLES_NE.NCS
NCS
UNC_R2_RxR_INSERTS.NCB
NCB
UNC_R2_RxR_INSERTS.NCS
NCS
UNC_R2_RxR_OCCUPANCY.DRS
DRS
UNC_R2_SBO0_CREDITS_ACQUIRED.AD
For AD Ring
UNC_R2_SBO0_CREDITS_ACQUIRED.BL
For BL Ring
UNC_R2_SBO0_CREDIT_OCCUPANCY.AD
For AD Ring
UNC_R2_SBO0_CREDIT_OCCUPANCY.BL
For BL Ring
UNC_R2_STALL_NO_SBO_CREDIT.SBO0_AD
For SBo0, AD Ring
UNC_R2_STALL_NO_SBO_CREDIT.SBO0_BL
For SBo0, BL Ring
UNC_R2_STALL_NO_SBO_CREDIT.SBO1_AD
For SBo1, AD Ring
UNC_R2_STALL_NO_SBO_CREDIT.SBO1_BL
For SBo1, BL Ring
UNC_R2_TxR_CYCLES_FULL.AD
AD
UNC_R2_TxR_CYCLES_FULL.AK
AK
UNC_R2_TxR_CYCLES_FULL.BL
BL
UNC_R2_TxR_CYCLES_NE.AD
AD
UNC_R2_TxR_CYCLES_NE.AK
AK
UNC_R2_TxR_CYCLES_NE.BL
BL
UNC_R2_TxR_NACK_CW.DN_AD
AD CCW
UNC_R2_TxR_NACK_CW.DN_AK
AK CCW
UNC_R2_TxR_NACK_CW.DN_BL
BL CCW
UNC_R2_TxR_NACK_CW.UP_AD
AK CCW
UNC_R2_TxR_NACK_CW.UP_AK
BL CW
UNC_R2_TxR_NACK_CW.UP_BL
BL CCW
UNC_R3_CLOCKTICKS
Number of uclks in domain
UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO10
CBox AD Credits Empty
UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO11
CBox AD Credits Empty
UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO12
CBox AD Credits Empty
UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO13
CBox AD Credits Empty
UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO14_16
CBox AD Credits Empty
UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO8
CBox AD Credits Empty
UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO9
CBox AD Credits Empty
UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO_15_17
CBox AD Credits Empty
UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO0
CBox AD Credits Empty
UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO1
CBox AD Credits Empty
UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO2
CBox AD Credits Empty
UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO3
CBox AD Credits Empty
UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO4
CBox AD Credits Empty
UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO5
CBox AD Credits Empty
UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO6
CBox AD Credits Empty
UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO7
CBox AD Credits Empty
UNC_R3_HA_R2_BL_CREDITS_EMPTY.HA0
HA/R2 AD Credits Empty
UNC_R3_HA_R2_BL_CREDITS_EMPTY.HA1
HA/R2 AD Credits Empty
UNC_R3_HA_R2_BL_CREDITS_EMPTY.R2_NCB
HA/R2 AD Credits Empty
UNC_R3_HA_R2_BL_CREDITS_EMPTY.R2_NCS
HA/R2 AD Credits Empty
UNC_R3_IOT_BACKPRESSURE.HUB
IOT Backpressure
UNC_R3_IOT_BACKPRESSURE.SAT
IOT Backpressure
UNC_R3_IOT_CTS_HI.CTS2
IOT Common Trigger Sequencer - Hi
UNC_R3_IOT_CTS_HI.CTS3
IOT Common Trigger Sequencer - Hi
UNC_R3_IOT_CTS_LO.CTS0
IOT Common Trigger Sequencer - Lo
UNC_R3_IOT_CTS_LO.CTS1
IOT Common Trigger Sequencer - Lo
UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_HOM
QPI0 AD Credits Empty
UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_NDR
QPI0 AD Credits Empty
UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_SNP
QPI0 AD Credits Empty
UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_HOM
QPI0 AD Credits Empty
UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_NDR
QPI0 AD Credits Empty
UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_SNP
QPI0 AD Credits Empty
UNC_R3_QPI0_AD_CREDITS_EMPTY.VNA
QPI0 AD Credits Empty
UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_HOM
QPI0 BL Credits Empty
UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_NDR
QPI0 BL Credits Empty
UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_SNP
QPI0 BL Credits Empty
UNC_R3_QPI0_BL_CREDITS_EMPTY.VNA
QPI0 BL Credits Empty
UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_HOM
QPI1 AD Credits Empty
UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_NDR
QPI1 AD Credits Empty
UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_SNP
QPI1 AD Credits Empty
UNC_R3_QPI1_AD_CREDITS_EMPTY.VNA
QPI1 AD Credits Empty
UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_HOM
QPI1 BL Credits Empty
UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_NDR
QPI1 BL Credits Empty
UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_SNP
QPI1 BL Credits Empty
UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_HOM
QPI1 BL Credits Empty
UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_NDR
QPI1 BL Credits Empty
UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_SNP
QPI1 BL Credits Empty
UNC_R3_QPI1_BL_CREDITS_EMPTY.VNA
QPI1 BL Credits Empty
UNC_R3_RING_AD_USED.CCW
Counterclockwise
UNC_R3_RING_AD_USED.CCW_EVEN
Counterclockwise and Even
UNC_R3_RING_AD_USED.CCW_ODD
Counterclockwise and Odd
UNC_R3_RING_AD_USED.CW
Clockwise
UNC_R3_RING_AD_USED.CW_EVEN
Clockwise and Even
UNC_R3_RING_AD_USED.CW_ODD
Clockwise and Odd
UNC_R3_RING_AK_USED.CCW
Counterclockwise
UNC_R3_RING_AK_USED.CCW_EVEN
Counterclockwise and Even
UNC_R3_RING_AK_USED.CCW_ODD
Counterclockwise and Odd
UNC_R3_RING_AK_USED.CW
Clockwise
UNC_R3_RING_AK_USED.CW_EVEN
Clockwise and Even
UNC_R3_RING_AK_USED.CW_ODD
Clockwise and Odd
UNC_R3_RING_BL_USED.CCW
Counterclockwise
UNC_R3_RING_BL_USED.CCW_EVEN
Counterclockwise and Even
UNC_R3_RING_BL_USED.CCW_ODD
Counterclockwise and Odd
UNC_R3_RING_BL_USED.CW
Clockwise
UNC_R3_RING_BL_USED.CW_EVEN
Clockwise and Even
UNC_R3_RING_BL_USED.CW_ODD
Clockwise and Odd
UNC_R3_RING_IV_USED.ANY
Any
UNC_R3_RING_IV_USED.CW
Clockwise
UNC_R3_RING_SINK_STARVED.AK
AK
UNC_R3_RxR_CYCLES_NE.HOM
HOM
UNC_R3_RxR_CYCLES_NE.NDR
NDR
UNC_R3_RxR_CYCLES_NE.SNP
SNP
UNC_R3_RxR_CYCLES_NE_VN1.DRS
DRS
UNC_R3_RxR_CYCLES_NE_VN1.HOM
HOM
UNC_R3_RxR_CYCLES_NE_VN1.NCB
NCB
UNC_R3_RxR_CYCLES_NE_VN1.NCS
NCS
UNC_R3_RxR_CYCLES_NE_VN1.NDR
NDR
UNC_R3_RxR_CYCLES_NE_VN1.SNP
SNP
UNC_R3_RxR_INSERTS.DRS
DRS
UNC_R3_RxR_INSERTS.HOM
HOM
UNC_R3_RxR_INSERTS.NCB
NCB
UNC_R3_RxR_INSERTS.NCS
NCS
UNC_R3_RxR_INSERTS.NDR
NDR
UNC_R3_RxR_INSERTS.SNP
SNP
UNC_R3_RxR_INSERTS_VN1.DRS
DRS
UNC_R3_RxR_INSERTS_VN1.HOM
HOM
UNC_R3_RxR_INSERTS_VN1.NCB
NCB
UNC_R3_RxR_INSERTS_VN1.NCS
NCS
UNC_R3_RxR_INSERTS_VN1.NDR
NDR
UNC_R3_RxR_INSERTS_VN1.SNP
SNP
UNC_R3_RxR_OCCUPANCY_VN1.DRS
DRS
UNC_R3_RxR_OCCUPANCY_VN1.HOM
HOM
UNC_R3_RxR_OCCUPANCY_VN1.NCB
NCB
UNC_R3_RxR_OCCUPANCY_VN1.NCS
NCS
UNC_R3_RxR_OCCUPANCY_VN1.NDR
NDR
UNC_R3_RxR_OCCUPANCY_VN1.SNP
SNP
UNC_R3_SBO0_CREDITS_ACQUIRED.AD
For AD Ring
UNC_R3_SBO0_CREDITS_ACQUIRED.BL
For BL Ring
UNC_R3_SBO0_CREDIT_OCCUPANCY.AD
For AD Ring
UNC_R3_SBO0_CREDIT_OCCUPANCY.BL
For BL Ring
UNC_R3_SBO1_CREDITS_ACQUIRED.AD
For AD Ring
UNC_R3_SBO1_CREDITS_ACQUIRED.BL
For BL Ring
UNC_R3_SBO1_CREDIT_OCCUPANCY.AD
For AD Ring
UNC_R3_SBO1_CREDIT_OCCUPANCY.BL
For BL Ring
UNC_R3_STALL_NO_SBO_CREDIT.SBO0_AD
For SBo0, AD Ring
UNC_R3_STALL_NO_SBO_CREDIT.SBO0_BL
For SBo0, BL Ring
UNC_R3_STALL_NO_SBO_CREDIT.SBO1_AD
For SBo1, AD Ring
UNC_R3_STALL_NO_SBO_CREDIT.SBO1_BL
For SBo1, BL Ring
UNC_R3_TxR_NACK.DN_AD
AD CCW
UNC_R3_TxR_NACK.DN_AK
AK CCW
UNC_R3_TxR_NACK.DN_BL
BL CCW
UNC_R3_TxR_NACK.UP_AD
AK CCW
UNC_R3_TxR_NACK.UP_AK
BL CW
UNC_R3_TxR_NACK.UP_BL
BL CCW
UNC_R3_VN0_CREDITS_REJECT.DRS
DRS Message Class
UNC_R3_VN0_CREDITS_REJECT.HOM
HOM Message Class
UNC_R3_VN0_CREDITS_REJECT.NCB
NCB Message Class
UNC_R3_VN0_CREDITS_REJECT.NCS
NCS Message Class
UNC_R3_VN0_CREDITS_REJECT.NDR
NDR Message Class
UNC_R3_VN0_CREDITS_REJECT.SNP
SNP Message Class
UNC_R3_VN0_CREDITS_USED.DRS
DRS Message Class
UNC_R3_VN0_CREDITS_USED.HOM
HOM Message Class
UNC_R3_VN0_CREDITS_USED.NCB
NCB Message Class
UNC_R3_VN0_CREDITS_USED.NCS
NCS Message Class
UNC_R3_VN0_CREDITS_USED.NDR
NDR Message Class
UNC_R3_VN0_CREDITS_USED.SNP
SNP Message Class
UNC_R3_VN1_CREDITS_REJECT.DRS
DRS Message Class
UNC_R3_VN1_CREDITS_REJECT.HOM
HOM Message Class
UNC_R3_VN1_CREDITS_REJECT.NCB
NCB Message Class
UNC_R3_VN1_CREDITS_REJECT.NCS
NCS Message Class
UNC_R3_VN1_CREDITS_REJECT.NDR
NDR Message Class
UNC_R3_VN1_CREDITS_REJECT.SNP
SNP Message Class
UNC_R3_VN1_CREDITS_USED.DRS
DRS Message Class
UNC_R3_VN1_CREDITS_USED.HOM
HOM Message Class
UNC_R3_VN1_CREDITS_USED.NCB
NCB Message Class
UNC_R3_VN1_CREDITS_USED.NCS
NCS Message Class
UNC_R3_VN1_CREDITS_USED.NDR
NDR Message Class
UNC_R3_VN1_CREDITS_USED.SNP
SNP Message Class
UNC_R3_VNA_CREDITS_ACQUIRED.AD
HOM Message Class
UNC_R3_VNA_CREDITS_ACQUIRED.BL
HOM Message Class
UNC_R3_VNA_CREDITS_REJECT.DRS
DRS Message Class
UNC_R3_VNA_CREDITS_REJECT.HOM
HOM Message Class
UNC_R3_VNA_CREDITS_REJECT.NCB
NCB Message Class
UNC_R3_VNA_CREDITS_REJECT.NCS
NCS Message Class
UNC_R3_VNA_CREDITS_REJECT.NDR
NDR Message Class
UNC_R3_VNA_CREDITS_REJECT.SNP
SNP Message Class
UNC_S_BOUNCE_CONTROL
Bounce Control
UNC_S_CLOCKTICKS
Uncore Clocks
UNC_S_FAST_ASSERTED
FaST wire asserted
UNC_S_RING_AD_USED.DOWN
Down
UNC_S_RING_AD_USED.DOWN_EVEN
Down and Event
UNC_S_RING_AD_USED.DOWN_ODD
Down and Odd
UNC_S_RING_AD_USED.UP_EVEN
Up and Even
UNC_S_RING_AD_USED.UP_ODD
Up and Odd
UNC_S_RING_AK_USED.DOWN
Down
UNC_S_RING_AK_USED.DOWN_EVEN
Down and Event
UNC_S_RING_AK_USED.DOWN_ODD
Down and Odd
UNC_S_RING_AK_USED.UP_EVEN
Up and Even
UNC_S_RING_AK_USED.UP_ODD
Up and Odd
UNC_S_RING_BL_USED.DOWN
Down
UNC_S_RING_BL_USED.DOWN_EVEN
Down and Event
UNC_S_RING_BL_USED.DOWN_ODD
Down and Odd
UNC_S_RING_BL_USED.UP_EVEN
Up and Even
UNC_S_RING_BL_USED.UP_ODD
Up and Odd
UNC_S_RING_BOUNCES.AD_CACHE
Number of LLC responses that bounced on the Ring.
UNC_S_RING_BOUNCES.AK_CORE
Acknowledgements to core
UNC_S_RING_BOUNCES.BL_CORE
Data Responses to core
UNC_S_RING_BOUNCES.IV_CORE
Snoops of processor's cache.
UNC_S_RING_IV_USED.DN
Any
UNC_S_RING_IV_USED.UP
Any
UNC_S_RING_SINK_STARVED.AD_CACHE
tbd
UNC_S_RING_SINK_STARVED.AK_CORE
tbd
UNC_S_RING_SINK_STARVED.BL_CORE
tbd
UNC_S_RING_SINK_STARVED.IV_CORE
tbd
UNC_S_RxR_BUSY_STARVED.AD_BNC
AD - Bounces
UNC_S_RxR_BUSY_STARVED.AD_CRD
AD - Credits
UNC_S_RxR_BUSY_STARVED.BL_BNC
BL - Bounces
UNC_S_RxR_BUSY_STARVED.BL_CRD
BL - Credits
UNC_S_RxR_BYPASS.AD_BNC
AD - Bounces
UNC_S_RxR_BYPASS.AD_CRD
AD - Credits
UNC_S_RxR_BYPASS.BL_BNC
BL - Bounces
UNC_S_RxR_BYPASS.BL_CRD
BL - Credits
UNC_S_RxR_CRD_STARVED.AD_BNC
AD - Bounces
UNC_S_RxR_CRD_STARVED.AD_CRD
AD - Credits
UNC_S_RxR_CRD_STARVED.AK
AK
UNC_S_RxR_CRD_STARVED.BL_BNC
BL - Bounces
UNC_S_RxR_CRD_STARVED.BL_CRD
BL - Credits
UNC_S_RxR_CRD_STARVED.IFV
IVF Credit
UNC_S_RxR_CRD_STARVED.IV
IV
UNC_S_RxR_INSERTS.AD_BNC
AD - Bounces
UNC_S_RxR_INSERTS.AD_CRD
AD - Credits
UNC_S_RxR_INSERTS.BL_BNC
BL - Bounces
UNC_S_RxR_INSERTS.BL_CRD
BL - Credits
UNC_S_RxR_OCCUPANCY.AD_BNC
AD - Bounces
UNC_S_RxR_OCCUPANCY.AD_CRD
AD - Credits
UNC_S_RxR_OCCUPANCY.AK
AK
UNC_S_RxR_OCCUPANCY.BL_BNC
BL - Bounces
UNC_S_RxR_OCCUPANCY.BL_CRD
BL - Credits
UNC_S_RxR_OCCUPANCY.IV
IV
UNC_S_TxR_ADS_USED.AD
tbd
UNC_S_TxR_ADS_USED.AK
tbd
UNC_S_TxR_ADS_USED.BL
tbd
UNC_S_TxR_INSERTS.AD_BNC
AD - Bounces
UNC_S_TxR_INSERTS.AD_CRD
AD - Credits
UNC_S_TxR_INSERTS.BL_BNC
BL - Bounces
UNC_S_TxR_INSERTS.BL_CRD
BL - Credits
UNC_S_TxR_OCCUPANCY.AD_BNC
AD - Bounces
UNC_S_TxR_OCCUPANCY.AD_CRD
AD - Credits
UNC_S_TxR_OCCUPANCY.AK
AK
UNC_S_TxR_OCCUPANCY.BL_BNC
BL - Bounces
UNC_S_TxR_OCCUPANCY.BL_CRD
BL - Credits
UNC_S_TxR_OCCUPANCY.IV
IV
UNC_S_TxR_STARVED.AD
Onto AD Ring
UNC_S_TxR_STARVED.AK
Onto AK Ring
UNC_S_TxR_STARVED.BL
Onto BL Ring
UNC_S_TxR_STARVED.IV
Onto IV Ring
UNC_U_EVENT_MSG.DOORBELL_RCVD
VLW Received
UNC_U_FILTER_MATCH.DISABLE
Filter Match
UNC_U_FILTER_MATCH.ENABLE
Filter Match
UNC_U_FILTER_MATCH.U2C_DISABLE
Filter Match
UNC_U_FILTER_MATCH.U2C_ENABLE
Filter Match
UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK
Assert to ACK
UNC_U_RACU_REQUESTS
RACU Request
UNC_U_U2C_EVENTS.CMC
Correctable Machine Check
UNC_U_U2C_EVENTS.LIVELOCK
Livelock
UNC_U_U2C_EVENTS.LTERROR
LTError
UNC_U_U2C_EVENTS.MONITOR_T0
Monitor T0
UNC_U_U2C_EVENTS.MONITOR_T1
Monitor T1
UNC_U_U2C_EVENTS.OTHER
Other
UNC_U_U2C_EVENTS.TRAP
Trap
UNC_U_U2C_EVENTS.UMC
Uncorrectable Machine Check
UOPS_DISPATCHED_PORT.PORT_0
Cycles per thread when uops are executed in port 0
UOPS_DISPATCHED_PORT.PORT_1
Cycles per thread when uops are executed in port 1
UOPS_DISPATCHED_PORT.PORT_2
Cycles per thread when uops are executed in port 2
UOPS_DISPATCHED_PORT.PORT_3
Cycles per thread when uops are executed in port 3
UOPS_DISPATCHED_PORT.PORT_4
Cycles per thread when uops are executed in port 4
UOPS_DISPATCHED_PORT.PORT_5
Cycles per thread when uops are executed in port 5
UOPS_DISPATCHED_PORT.PORT_6
Cycles per thread when uops are executed in port 6
UOPS_DISPATCHED_PORT.PORT_7
Cycles per thread when uops are executed in port 7
UOPS_EXECUTED.CORE
Number of uops executed on the core.
UOPS_EXECUTED.CORE_CYCLES_GE_1
Cycles at least 1 micro-op is executed from any thread on physical core
UOPS_EXECUTED.CORE_CYCLES_GE_2
Cycles at least 2 micro-op is executed from any thread on physical core
UOPS_EXECUTED.CORE_CYCLES_GE_3
Cycles at least 3 micro-op is executed from any thread on physical core
UOPS_EXECUTED.CORE_CYCLES_GE_4
Cycles at least 4 micro-op is executed from any thread on physical core
UOPS_EXECUTED.CORE_CYCLES_NONE
Cycles with no micro-ops executed from any thread on physical core
UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC
This events counts the cycles where at least one uop was executed. It is counted per thread.
UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC
This events counts the cycles where at least two uop were executed. It is counted per thread.
UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC
This events counts the cycles where at least three uop were executed. It is counted per thread.
UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC
Cycles where at least 4 uops were executed per-thread
UOPS_EXECUTED.STALL_CYCLES
Counts number of cycles no uops were dispatched to be executed on this thread.
UOPS_EXECUTED_PORT.PORT_0
Cycles per thread when uops are executed in port 0
UOPS_EXECUTED_PORT.PORT_0_CORE
Cycles per core when uops are exectuted in port 0
UOPS_EXECUTED_PORT.PORT_1
Cycles per thread when uops are executed in port 1
UOPS_EXECUTED_PORT.PORT_1_CORE
Cycles per core when uops are exectuted in port 1
UOPS_EXECUTED_PORT.PORT_2
Cycles per thread when uops are executed in port 2
UOPS_EXECUTED_PORT.PORT_2_CORE
Cycles per core when uops are dispatched to port 2
UOPS_EXECUTED_PORT.PORT_3
Cycles per thread when uops are executed in port 3
UOPS_EXECUTED_PORT.PORT_3_CORE
Cycles per core when uops are dispatched to port 3
UOPS_EXECUTED_PORT.PORT_4
Cycles per thread when uops are executed in port 4
UOPS_EXECUTED_PORT.PORT_4_CORE
Cycles per core when uops are exectuted in port 4
UOPS_EXECUTED_PORT.PORT_5
Cycles per thread when uops are executed in port 5
UOPS_EXECUTED_PORT.PORT_5_CORE
Cycles per core when uops are exectuted in port 5
UOPS_EXECUTED_PORT.PORT_6
Cycles per thread when uops are executed in port 6
UOPS_EXECUTED_PORT.PORT_6_CORE
Cycles per core when uops are exectuted in port 6
UOPS_EXECUTED_PORT.PORT_7
Cycles per thread when uops are executed in port 7
UOPS_EXECUTED_PORT.PORT_7_CORE
Cycles per core when uops are dispatched to port 7
UOPS_ISSUED.ANY
This event counts the number of uops issued by the Front-end of the pipeline to the Back-end. This event is counted at the allocation stage and will count both retired and non-retired uops.
UOPS_ISSUED.CORE_STALL_CYCLES
Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads
UOPS_ISSUED.FLAGS_MERGE
Number of flags-merge uops being allocated. Such uops considered perf sensitive; added by GSR u-arch.
UOPS_ISSUED.SINGLE_MUL
Number of Multiply packed/scalar single precision uops allocated
UOPS_ISSUED.SLOW_LEA
Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.
UOPS_ISSUED.STALL_CYCLES
Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread
UOPS_RETIRED.ALL
Actually retired uops.
UOPS_RETIRED.ALL_PS
Actually retired uops.
UOPS_RETIRED.CORE_STALL_CYCLES
Cycles without actually retired uops.
UOPS_RETIRED.RETIRE_SLOTS
This event counts the number of retirement slots used each cycle. There are potentially 4 slots that can be used each cycle - meaning, 4 uops or 4 instructions could retire each cycle.
UOPS_RETIRED.RETIRE_SLOTS_PS
Retirement slots used.
UOPS_RETIRED.STALL_CYCLES
Cycles without actually retired uops.
UOPS_RETIRED.TOTAL_CYCLES
Cycles with less than 10 actually retired uops.