Intel® VTune™ Amplifier
This section provides reference for hardware events that can be monitored for the CPU(s):
The following performance-monitoring events are supported:
Cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations.
Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.
number of near branch instructions retired that were mispredicted and taken.
number of near branch instructions retired that were mispredicted and taken.
Count XClk pulses when this thread is unhalted and the other thread is halted.
Reference cycles when the thread is unhalted (counts at 100 MHz rate)
Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate)
Core cycles when at least one thread on the physical core is not in halt state
Core cycles when at least one thread on the physical core is not in halt state
Load miss in all TLB levels causes a page walk that completes. (All page sizes)
Counts 1 per cycle for each PMH that is busy with a page walk for a load.
Store misses in all TLB levels causes a page walk that completes. (All page sizes)
Counts 1 per cycle for each PMH that is busy with a page walk for a store.
Counts 1 per cycle for each PMH that is busy with a EPT (Extended Page Table) walk for any request type.
Cycles total of 1 uop is executed on all ports and Reservation Station was not empty.
Cycles total of 2 uops are executed on all ports and Reservation Station was not empty.
Cycles total of 3 uops are executed on all ports and Reservation Station was not empty.
Cycles total of 4 uops are executed on all ports and Reservation Station was not empty.
Cycles where no uops were executed, the Reservation Station was not empty, the Store Buffer was full and there was no outstanding load.
Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired. Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.
Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.
Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.
Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired. Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.
Number of SSE/AVX computational scalar double precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.
Number of SSE/AVX computational scalar single precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.
Retired Instructions who experienced decode stream buffer (DSB - the decoded insturction-cache) miss.
Retired Instructions who experienced decode stream buffer (DSB - the decoded insturction-cache) miss. Precise Event.
Retired Instructions who experienced Instruction L1 Cache true miss. Precise Event.
Retired Instructions who experienced Instruction L2 Cache true miss. Precise Event.
Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.
Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall. Precise Event.
Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.
Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall. Precise Event.
Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 2 cycles which was not interrupted by a back-end stall.
Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall
Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall. Precise Event.
Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.
Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall. Precise Event.
Retired instructions that are fetched after an interval where the front-end had at least 2 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall.
Retired instructions that are fetched after an interval where the front-end had at least 2 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall. Precise Event.
Retired instructions that are fetched after an interval where the front-end had at least 3 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall.
Retired instructions that are fetched after an interval where the front-end had at least 3 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall. Precise Event.
Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 2 cycles which was not interrupted by a back-end stall. Precise Event.
Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.
Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall. Precise Event.
Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.
Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall. Precise Event.
Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.
Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall. Precise Event.
Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.
Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall. Precise Event
Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.
Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.
Retired Instructions who experienced STLB (2nd level TLB) true miss. Precise Event.
Number of times an HLE execution aborted due to any reasons (multiple categories may count as one).
Number of times an HLE execution aborted due to any reasons (multiple categories may count as one).
Number of times an HLE execution aborted due to unfriendly events (such as interrupts).
Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).
Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).
Instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity.
Instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity.
Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path
Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path
Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path
Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy
Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy
Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy
Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer
Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled
Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled
Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.
Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled
Cycles with less than 2 uops delivered by the front end.
Cycles with less than 3 uops delivered by the front end.
Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution
Number of cycles using always true condition applied to PEBS instructions retired event.
Cycles the issue-stage is waiting for front-end to fetch from resteered path following branch misprediction or machine clear events.
Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke)
Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke)
Code miss in all TLB levels causes a page walk that completes. (All page sizes)
Counts 1 per cycle for each PMH that is busy with a page walk for an instruction fetch request.
Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch. HWP are e
Cycles with L1D load Misses outstanding from any thread on physical core
Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cache
Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that miss L2 cache
The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use
Demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch.
Number of load instructions retired with cache-line splits that may impact performance.
Number of load instructions retired with cache-line splits that may impact performance. Precise Event.
Retired load instructions which data sources were L3 and cross-core snoop hits in on-pkg core cache
Retired load instructions which data sources were HitM responses from shared L3
Retired load instructions which data sources were HitM responses from shared L3
Retired load instructions which data sources were L3 and cross-core snoop hits in on-pkg core cache
Retired load instructions which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.
Retired load instructions which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.
Retired load instructions which data sources were hits in L3 without snoops required
Retired load instructions which data sources were hits in L3 without snoops required
Retired load instructions which data sources were load missed L1 but hit FB due to preceding miss to the same cache line with data not ready
Retired load instructions which data sources were load missed L1 but hit FB due to preceding miss to the same cache line with data not ready
Counts loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.
Counts loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.
Counts loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.
Counts loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.
Counts loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.
Counts loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.
Counts loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.
Counts loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.
Offcore requests buffer cannot take more entries for this thread core.
Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore
Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore
Cycles with offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore, every cycle.
Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore
Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle
Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ
Cycles with offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore, every cycle.
Offcore outstanding Demand Data Read transactions in uncore queue.
Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue
Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle
Counts number of Offcore outstanding Demand Data Read requests who miss L3 cache in the superQ every cycle.
Cycles with at least 6 Demand Data Read requests who miss L3 cache in the superQ
Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction
Number of times a microcode assist is invoked by HW other than FP-assist. Examples include AD (page Access Dirty) and AVX* related assists.
Cycles stalled due to no store buffers available. (not including draining form sync).
Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.
Number of times an RTM execution aborted due to any reasons (multiple categories may count as one).
Number of times an RTM execution aborted due to any reasons (multiple categories may count as one).
Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)
Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)
Number of times an RTM execution aborted due to HLE-unfriendly instructions
Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.
Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region
Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded
Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.
Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region
Number of times a transactional abort was signaled due to a data capacity limitation for transactional reads or writes.
Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address
Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer
Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.
Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.
Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer
Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.
Cycles at least 1 micro-op is executed from any thread on physical core
Cycles at least 2 micro-op is executed from any thread on physical core
Cycles at least 3 micro-op is executed from any thread on physical core
Cycles at least 4 micro-op is executed from any thread on physical core
Counts number of cycles no uops were dispatched to be executed on this thread.
Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.
Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread
This event counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to ?Mixing Intel AVX and Intel SSE Code? section of the Optimization Guide.