Intel® VTune™ Amplifier
This section provides reference for hardware events that can be monitored for the CPU(s):
The following performance-monitoring events are supported:
This event counts executed load operations with all the following traits: 1. addressing of the format [base + offset], 2. the offset is between 1 and 2047, 3. the address specified in the base register is in one page and the address [base+offset] is in an
Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.
Speculative and retired macro-unconditional branches excluding calls and indirects
Speculative and retired indirect branches excluding calls and returns
Taken speculative and retired macro-conditional branch instructions excluding calls and indirects
Taken speculative and retired indirect branches excluding calls and returns
Taken speculative and retired indirect branches with return mnemonic
Direct and indirect near call instructions retired. (Precise Event - PEBS)
Direct and indirect macro near call instructions retired (captured in ring 3).
Direct and indirect macro near call instructions retired (captured in ring 3). (Precise Event - PEBS)
Mispredicted indirect branches excluding calls and returns
Not taken speculative and retired mispredicted macro conditional branches
Taken speculative and retired mispredicted macro conditional branches
Taken speculative and retired mispredicted indirect branches excluding calls and returns
Taken speculative and retired mispredicted indirect branches with return mnemonic
Mispredicted macro branch instructions retired. (Precise Event - PEBS)
Mispredicted conditional branch instructions retired. (Precise Event - PEBS)
Direct and indirect mispredicted near call instructions retired. (Precise Event - PEBS)
Mispredicted not taken branch instructions retired.(Precise Event - PEBS)
Count XClk pulses when this thread is unhalted and the other is halted.
Reference cycles when the thread is unhalted (counts at 100 MHz rate)
Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate)
This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.
This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.
Core cycles when at least one thread on the physical core is not in halt state
Core cycles when at least one thread on the physical core is not in halt state
Each cycle there was a miss-pending demand load this thread, increment by 1. Note this is in DCU and connected to Umask 1. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING.
Each cycle there was a MLC-miss pending demand load this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0.
Each cycle there was no dispatch for this thread, increment by 1. Note this is connect to Umask 2. No dispatch can be deduced from the UOPS_EXECUTED event.
Each cycle there was a miss-pending demand load this thread and no uops dispatched, increment by 1. Note this is in DCU and connected to Umask 1 and 2. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING.
Each cycle there was a MLC-miss pending demand load and no uops dispatched on this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0 and 2.
This event counts the cycles attributed to a switch from the Decoded Stream Buffer (DSB), which holds decoded instructions, to the legacy decode pipeline. It excludes cycles when the back-end cannot accept new micro-ops. The penalty for these switches is potentially several cycles of instruction starvation, where no micro-ops are delivered to the back-end.
Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exceeding way limit
Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines
This event counts load operations that miss the first DTLB level but hit the second and do not cause any page walks. The penalty in this case is approximately 7 cycles.
This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses.
Store operations that miss the first TLB level but hit the second and do not cause page walks
Cycle count for an Extended Page table walk. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.
Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle
Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle
Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle
Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle
Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s
Hardware Prefetch requests that miss the L1D cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for
Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches
This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes unchacheable accesses.
Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path
Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path
Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path
This event counts cycles during which the microcode sequencer assisted the front-end in delivering uops. Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder. Using other instructions, if possible, will usually improve performance. See the Intel? 64 and IA-32 Architectures Optimization Reference Manual for more information.
Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy
Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy
Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy
Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy
Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer
This event counts the number of uops not delivered to the back-end per cycle, per thread, when the back-end was not stalled. In the ideal case 4 uops can be delivered each cycle. The event counts the undelivered uops - so if 3 were delivered in one cycle, the counter would be incremented by 1 for that cycle (4 - 3). If the back-end is stalled, the count for this event is not incremented even when uops were not delivered, because the back-end would not have been able to accept them. This event is used in determining the front-end bound category of the top-down pipeline slots characterization.
Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled
Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.
Cycles when 1 or more uops were delivered to the by the front end.
Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled
Cycles with less than 2 uops delivered by the front end
Cycles with less than 3 uops delivered by the front end
This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers.
Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread
Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)
Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke)
Number of occurences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)
Operations that miss the first ITLB level but hit the second and do not cause any page walks
This event count cycles when Page Miss Handler (PMH) is servicing page walks caused by ITLB misses.
Cache lines in M state evicted out of L1D due to Snoop HitM or dirty line replacement
This event counts L1D data line replacements. Replacements occur when a new line is brought into the cache, causing eviction of a line loaded earlier.
Cycles when dispatched loads are cancelled due to L1D bank conflicts with other load ports
Cycles with L1D load Misses outstanding from any thread on physical core
Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.)
This event counts the number of L2 cache lines brought into the L2 cache. Lines are filled into the L2 cache when there was an L2 miss.
Number of cases where any load ends up with a valid block-code written to the load buffer (including blocks due to Memory Order Buffer (MOB), Data Cache Unit (DCU), TLB, but load has no DCU miss)
Loads delayed due to SB blocks, preceding store operations with known addresses but unknown data
This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.
This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceeding smaller uncompleted store. See the table of not supported store forwards in the Intel? 64 and IA-32 Architectures Optimization Reference Manual. The penalty for blocked store forwarding is that the load must wait for the store to complete before it can be issued.
Aliasing occurs when a load is issued after a store and their memory addresses are offset by 4K. This event counts the number of loads that aliased with a preceding store, resulting in an extended address check in the pipeline. The enhanced address check typically has a performance penalty of 5 cycles.
This event counts the number of times that load operations are temporarily blocked because of older stores, with addresses that are not yet known. A load operation may incur more than one block of this type.
Not software-prefetch load dispatches that hit FB allocated for hardware prefetch
Not software-prefetch load dispatches that hit FB allocated for software prefetch
Maskmov false fault - counts number of time ucode passes through Maskmov flow due to instruction's mask being 0 while the flow was completed without raising a fault.
This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from memory disambiguation, external snoops, or cross SMT-HW-thread snoop (stores) hitting load buffers. Machine clears can have a significant performance impact if they are happening frequently.
This event is incremented when self-modifying code (SMC) is detected, which causes a machine clear. Machine clears can have a significant performance impact if they are happening frequently.
This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package). Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line. In this case, a snoop was required, and another L2 had the line in a non-modified state.
This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package). Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line. In this case, a snoop was required, and another L2 had the line in a modified state, so the line had to be invalidated in that L2 cache and transferred to the requesting L2.
This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package). Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line. In this case, a snoop was required, and another L2 had the line in a modified state, so the line had to be invalidated in that L2 cache and transferred to the requesting L2. (Precise Event - PEBS)
This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package). Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line. In this case, a snoop was required, and another L2 had the line in a non-modified state. (Precise Event - PEBS)
Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache.
Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache. (Precise Event - PEBS)
Retired load uops which data sources were hits in LLC without snoops required.
Retired load uops which data sources were hits in LLC without snoops required. (Precise Event - PEBS)
This event counts retired demand loads that missed the last-level (L3) cache. This means that the load is usually satisfied from memory in a client system or possibly from the remote socket in a server. Demand loads are non speculative load uops.
This event counts retired demand loads that missed the last-level (L3) cache. This means that the load is usually satisfied from memory in a client system or possibly from the remote socket in a server. Demand loads are non speculative load uops. (Precise Event - PEBS)
Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.
Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. (Precise Event - PEBS)
Retired load uops with L1 cache hits as data sources. (Precise Event - PEBS)
Retired load uops with L2 cache hits as data sources. (Precise Event - PEBS)
This event counts retired load uops that hit in the last-level (L3) cache without snoops required.
This event counts retired load uops that hit in the last-level (L3) cache without snoops required. (Precise Event - PEBS)
Sample stores and collect precise store operation via PEBS record. PMC3 only. (Precise Event - PEBS)
This event counts the number of store uops retired. (Precise Event - PEBS)
This event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).
This event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K). (Precise Event - PEBS)
This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).
This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K). (Precise Event - PEBS)
Cases when offcore requests buffer cannot take more entries for core
Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore
Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore
Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore
Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle
Offcore outstanding Demand Data Read transactions in uncore queue.
Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue
Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore
Counts all demand & prefetch code reads that hit in the LLC
Counts demand & prefetch code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts demand & prefetch code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts demand & prefetch code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts demand & prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts demand & prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts demand & prefetch code reads that hit in the LLC and the snoops sent to sibling cores return clean response
Counts demand & prefetch code reads that hit in the LLC and the snoops sent to sibling cores return clean response
Counts all demand & prefetch code reads that miss the LLC and the data returned from dram
Counts all demand & prefetch code reads that miss the LLC and the data returned from dram
Counts all demand & prefetch data reads that hit in the LLC
Counts all demand & prefetch data reads that hit in the LLC
Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts demand & prefetch data reads that hit in the LLC and the snoops sent to sibling cores return clean response
Counts demand & prefetch data reads that hit in the LLC and the snoops sent to sibling cores return clean response
Counts all demand & prefetch data reads that miss the LLC and the data returned from dram
Counts all demand & prefetch data reads that miss the LLC and the data returned from dram
Counts all prefetch code reads that hit in the LLC
Counts all prefetch code reads that hit in the LLC
Counts prefetch code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts prefetch code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts prefetch code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts prefetch code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts prefetch code reads that hit in the LLC and the snoops sent to sibling cores return clean response
Counts prefetch code reads that hit in the LLC and the snoops sent to sibling cores return clean response
Counts all prefetch code reads that miss the LLC and the data returned from dram
Counts all prefetch code reads that miss the LLC and the data returned from dram
Counts all prefetch data reads that hit in the LLC
Counts all prefetch data reads that hit in the LLC
Counts prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts prefetch data reads that hit in the LLC and the snoops sent to sibling cores return clean response
Counts prefetch data reads that hit in the LLC and the snoops sent to sibling cores return clean response
Counts all prefetch data reads that miss the LLC and the data returned from dram
Counts all prefetch data reads that miss the LLC and the data returned from dram
Counts prefetch RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts prefetch RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts prefetch RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts prefetch RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts prefetch RFOs that hit in the LLC and the snoops sent to sibling cores return clean response
Counts prefetch RFOs that hit in the LLC and the snoops sent to sibling cores return clean response
Counts all prefetch RFOs that miss the LLC and the data returned from dram
Counts all prefetch RFOs that miss the LLC and the data returned from dram
Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC
Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC
Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops sent to sibling cores return clean response
Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops sent to sibling cores return clean response
Counts all data/code/rfo reads (demand & prefetch) that miss the LLC and the data returned from dram
Counts all data/code/rfo reads (demand & prefetch) that miss the LLC and the data returned from dram
Counts all data/code/rfo references (demand & prefetch) made to LLC that either hit or miss the LLC
Counts all data/code/rfo references (demand & prefetch) made to LLC that either hit or miss the LLC
Counts all demand & prefetch RFOs that hit in the LLC
Counts all demand & prefetch RFOs that hit in the LLC
Counts demand & prefetch RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts demand & prefetch RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts demand & prefetch RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts demand & prefetch RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts demand & prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts demand & prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts demand & prefetch RFOs that hit in the LLC and the snoops sent to sibling cores return clean response
Counts demand & prefetch RFOs that hit in the LLC and the snoops sent to sibling cores return clean response
Counts all demand & prefetch RFOs that miss the LLC and the data returned from dram
Counts all demand & prefetch RFOs that miss the LLC and the data returned from dram
This event counts any requests that miss the LLC where the data was returned from local DRAM
This event counts any requests that miss the LLC where the data was returned from local DRAM
This event counts all data requests (demand/prefetch data reads and demand data writes (RFOs) that miss the LLC where the data is returned from local DRAM
This event counts all data requests (demand/prefetch data reads and demand data writes (RFOs) that miss the LLC where the data is returned from local DRAM
REQUEST = DATA_IN_SOCKET and RESPONSE = LLC_MISS_LOCAL and SNOOP = ANY_LLC_HIT
REQUEST = DATA_IN_SOCKET and RESPONSE = LLC_MISS_LOCAL and SNOOP = ANY_LLC_HIT
Counts all demand code reads that hit in the LLC
Counts all demand code reads that hit in the LLC
Counts demand code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts demand code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts demand code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts demand code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts demand code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts demand code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts demand code reads that hit in the LLC and the snoops sent to sibling cores return clean response
Counts demand code reads that hit in the LLC and the snoops sent to sibling cores return clean response
Counts demand code reads that miss the LLC and the data returned from dram
Counts demand code reads that miss the LLC and the data returned from dram
Counts all demand data reads that hit in the LLC
Counts all demand data reads that hit in the LLC
Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts demand data reads that hit in the LLC and the snoops sent to sibling cores return clean response
Counts demand data reads that hit in the LLC and the snoops sent to sibling cores return clean response
Counts demand data reads that miss the LLC and the data returned from dram
Counts demand data reads that miss the LLC and the data returned from dram
REQUEST = DEMAND_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM
REQUEST = DEMAND_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM
Counts all demand data writes (RFOs) that hit in the LLC
Counts all demand data writes (RFOs) that hit in the LLC
Counts demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts demand data writes (RFOs) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts demand data writes (RFOs) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts demand data writes (RFOs) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts demand data writes (RFOs) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts demand data writes (RFOs) that hit in the LLC and the snoops sent to sibling cores return clean response
Counts demand data writes (RFOs) that hit in the LLC and the snoops sent to sibling cores return clean response
REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_M and SNOOP = HITM
REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_M and SNOOP = HITM
Counts demand data writes (RFOs) that miss the LLC and the data returned from dram
Counts demand data writes (RFOs) that miss the LLC and the data returned from dram
Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses. It also includes L2 hints sent to LLC to keep a line from being evicted out of the core caches
Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses. It also includes L2 hints sent to LLC to keep a line from being evicted out of the core caches
Counts L2 hints sent to LLC to keep a line from being evicted out of the core caches
Counts L2 hints sent to LLC to keep a line from being evicted out of the core caches
Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses
Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses
REQUEST = PF_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM
REQUEST = PF_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM
REQUEST = PF_RFO and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM
REQUEST = PF_RFO and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM
Counts all prefetch (that bring data to L2) code reads that hit in the LLC
Counts all prefetch (that bring data to L2) code reads that hit in the LLC
Counts prefetch (that bring data to L2) code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts prefetch (that bring data to L2) code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts prefetch (that bring data to L2) code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts prefetch (that bring data to L2) code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts prefetch (that bring data to L2) code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts prefetch (that bring data to L2) code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts prefetch (that bring data to L2) code reads that hit in the LLC and the snoops sent to sibling cores return clean response
Counts prefetch (that bring data to L2) code reads that hit in the LLC and the snoops sent to sibling cores return clean response
Counts all prefetch (that bring data to L2) code reads that miss the LLC and the data returned from dram
Counts all prefetch (that bring data to L2) code reads that miss the LLC and the data returned from dram
Counts all prefetch (that bring data to L2) data reads that hit in the LLC
Counts all prefetch (that bring data to L2) data reads that hit in the LLC
Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts prefetch (that bring data to L2) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts prefetch (that bring data to L2) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops sent to sibling cores return clean response
Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops sent to sibling cores return clean response
Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from dram
Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from dram
Counts all prefetch (that bring data to L2) RFOs that hit in the LLC
Counts all prefetch (that bring data to L2) RFOs that hit in the LLC
Counts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts prefetch (that bring data to L2) RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts prefetch (that bring data to L2) RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoops sent to sibling cores return clean response
Counts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoops sent to sibling cores return clean response
Counts all prefetch (that bring data to L2) RFOs that miss the LLC and the data returned from dram
Counts all prefetch (that bring data to L2) RFOs that miss the LLC and the data returned from dram
Counts all prefetch (that bring data to LLC only) code reads that hit in the LLC
Counts all prefetch (that bring data to LLC only) code reads that hit in the LLC
Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoops sent to sibling cores return clean response
Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoops sent to sibling cores return clean response
Counts all prefetch (that bring data to LLC only) code reads that miss the LLC and the data returned from dram
Counts all prefetch (that bring data to LLC only) code reads that miss the LLC and the data returned from dram
Counts all prefetch (that bring data to LLC only) data reads that hit in the LLC
Counts all prefetch (that bring data to LLC only) data reads that hit in the LLC
Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response
Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response
Counts all prefetch (that bring data to LLC only) data reads that miss the LLC and the data returned from dram
Counts all prefetch (that bring data to LLC only) data reads that miss the LLC and the data returned from dram
Counts all prefetch (that bring data to LLC only) RFOs that hit in the LLC
Counts all prefetch (that bring data to LLC only) RFOs that hit in the LLC
Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoops sent to sibling cores return clean response
Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoops sent to sibling cores return clean response
Counts all prefetch (that bring data to LLC only) RFOs that miss the LLC and the data returned from dram
Counts all prefetch (that bring data to LLC only) RFOs that miss the LLC and the data returned from dram
REQUEST = PF_LLC_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM
REQUEST = PF_LLC_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM
REQUEST = PF_LLC_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM
REQUEST = PF_LLC_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM
Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address
Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address
Counts all demand & prefetch code reads that hit in the LLC
Counts all demand & prefetch code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts all demand & prefetch code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts all demand & prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts all demand & prefetch code reads that hit in the LLC and the snoops sent to sibling cores return clean response
Counts all demand & prefetch code reads that miss the LLC and the data returned from local or remote dram
Counts all demand & prefetch code reads that miss in the LLC
Counts all demand & prefetch code reads that miss the LLC and the data returned from local dram
Counts all demand & prefetch data reads that hit in the LLC
Counts all demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts all demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts all demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts all demand & prefetch data reads that hit in the LLC and the snoops sent to sibling cores return clean response
Counts all demand & prefetch data reads that miss the LLC and the data returned from local or remote dram
Counts all demand & prefetch data reads that miss in the LLC
Counts all demand & prefetch data reads that miss the LLC and the data returned from local dram
Counts all prefetch code reads that hit in the LLC
Counts all prefetch code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts all prefetch code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts all prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts all prefetch code reads that hit in the LLC and the snoops sent to sibling cores return clean response
Counts all prefetch code reads that miss the LLC and the data returned from local or remote dram
Counts all prefetch code reads that miss in the LLC
Counts all prefetch code reads that miss the LLC and the data returned from local dram
Counts all prefetch data reads that hit in the LLC
Counts all prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts all prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts all prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts all prefetch data reads that hit in the LLC and the snoops sent to sibling cores return clean response
Counts all prefetch data reads that miss the LLC and the data returned from local or remote dram
Counts all prefetch data reads that miss in the LLC
Counts all prefetch data reads that miss the LLC and the data returned from local dram
Counts prefetch RFOs that hit in the LLC
Counts prefetch RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts prefetch RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts prefetch RFOs that hit in the LLC and the snoops sent to sibling cores return clean response
Counts prefetch RFOs that miss the LLC and the data returned from local or remote dram
Counts prefetch RFOs that miss in the LLC
Counts prefetch RFOs that miss the LLC and the data returned from local dram
Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC
Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops sent to sibling cores return clean response
Counts all data/code/rfo reads (demand & prefetch) that miss the LLC and the data returned from local or remote dram
Counts all data/code/rfo reads (demand & prefetch) that miss in the LLC
Counts all data/code/rfo reads (demand & prefetch) that miss the LLC and the data returned from local dram
Counts all requests that hit in the LLC
Counts all requests that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts all requests that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts all requests that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts all requests that hit in the LLC and the snoops sent to sibling cores return clean response
Counts all requests that miss the LLC and the data returned from local or remote dram
Counts all requests that miss in the LLC
Counts all requests that miss the LLC and the data returned from local dram
Counts all demand & prefetch RFOs that hit in the LLC
Counts all demand & prefetch RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts all demand & prefetch RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts all demand & prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts all demand & prefetch RFOs that hit in the LLC and the snoops sent to sibling cores return clean response
Counts all demand & prefetch RFOs that miss the LLC and the data returned from local or remote dram
Counts all demand & prefetch RFOs that miss in the LLC
Counts all demand & prefetch RFOs that miss the LLC and the data returned from local dram
Counts core writebacks due to L2 evictions or L1 writeback requests that hit in the LLC
Counts core writebacks due to L2 evictions or L1 writeback requests that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts core writebacks due to L2 evictions or L1 writeback requests that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts core writebacks due to L2 evictions or L1 writeback requests that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts core writebacks due to L2 evictions or L1 writeback requests that hit in the LLC and the snoops sent to sibling cores return clean response
Counts core writebacks due to L2 evictions or L1 writeback requests that miss the LLC and the data returned from local or remote dram
Counts core writebacks due to L2 evictions or L1 writeback requests that miss in the LLC
Counts core writebacks due to L2 evictions or L1 writeback requests that miss the LLC and the data returned from local dram
Counts all demand code reads that hit in the LLC
Counts all demand code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts all demand code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts all demand code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts all demand code reads that hit in the LLC and the snoops sent to sibling cores return clean response
Counts all demand code reads that miss the LLC and the data returned from local or remote dram
Counts all demand code reads that miss in the LLC
Counts all demand code reads that miss the LLC and the data returned from local dram
Counts demand data reads that hit in the LLC
Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts demand data reads that hit in the LLC and the snoops sent to sibling cores return clean response
Counts demand data reads that miss the LLC and the data returned from local or remote dram
Counts demand data reads that miss in the LLC
Counts demand data reads that miss the LLC and the data returned from local dram
Counts all demand data writes (RFOs) that hit in the LLC
Counts all demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts all demand data writes (RFOs) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts all demand data writes (RFOs) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts all demand data writes (RFOs) that hit in the LLC and the snoops sent to sibling cores return clean response
Counts all demand data writes (RFOs) that miss the LLC and the data returned from local or remote dram
Counts all demand data writes (RFOs) that miss in the LLC
Counts all demand data writes (RFOs) that miss the LLC and the data returned from local dram
Counts any other requests that hit in the LLC
Counts any other requests that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts any other requests that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts any other requests that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts any other requests that hit in the LLC and the snoops sent to sibling cores return clean response
Counts any other requests that miss the LLC and the data returned from local or remote dram
Counts any other requests that miss in the LLC
Counts any other requests that miss the LLC and the data returned from local dram
Counts all prefetch (that bring data to LLC only) code reads that hit in the LLC
Counts all prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts all prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts all prefetch (that bring data to LLC only) code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts all prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoops sent to sibling cores return clean response
Counts all prefetch (that bring data to LLC only) code reads that miss the LLC and the data returned from local or remote dram
Counts all prefetch (that bring data to LLC only) code reads that miss in the LLC
Counts all prefetch (that bring data to LLC only) code reads that miss the LLC and the data returned from local dram
Counts prefetch (that bring data to L2) data reads that hit in the LLC
Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts prefetch (that bring data to L2) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops sent to sibling cores return clean response
Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from local or remote dram
Counts prefetch (that bring data to L2) data reads that miss in the LLC
Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from local dram
Counts all prefetch (that bring data to L2) RFOs that hit in the LLC
Counts all prefetch (that bring data to L2) RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts all prefetch (that bring data to L2) RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts all prefetch (that bring data to L2) RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts all prefetch (that bring data to L2) RFOs that hit in the LLC and the snoops sent to sibling cores return clean response
Counts all prefetch (that bring data to L2) RFOs that miss the LLC and the data returned from local or remote dram
Counts all prefetch (that bring data to L2) RFOs that miss in the LLC
Counts all prefetch (that bring data to L2) RFOs that miss the LLC and the data returned from local dram
Counts prefetch (that bring data to LLC only) code reads that hit in the LLC
Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoops sent to sibling cores return clean response
Counts prefetch (that bring data to LLC only) code reads that miss the LLC and the data returned from local or remote dram
Counts prefetch (that bring data to LLC only) code reads that miss in the LLC
Counts prefetch (that bring data to LLC only) code reads that miss the LLC and the data returned from local dram
Counts all prefetch (that bring data to LLC only) data reads that hit in the LLC
Counts all prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts all prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts all prefetch (that bring data to LLC only) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts all prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response
Counts all prefetch (that bring data to LLC only) data reads that miss the LLC and the data returned from local or remote dram
Counts all prefetch (that bring data to LLC only) data reads that miss in the LLC
Counts all prefetch (that bring data to LLC only) data reads that miss the LLC and the data returned from local dram
Counts all prefetch (that bring data to LLC only) RFOs that hit in the LLC
Counts all prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded
Counts all prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded
Counts all prefetch (that bring data to LLC only) RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores
Counts all prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoops sent to sibling cores return clean response
Counts all prefetch (that bring data to LLC only) RFOs that miss the LLC and the data returned from local or remote dram
Counts all prefetch (that bring data to LLC only) RFOs that miss in the LLC
Counts all prefetch (that bring data to LLC only) RFOs that miss the LLC and the data returned from local dram
Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations.
Number of any page walk that had a miss in LLC. Does not necessary cause a SUSPEND
This event counts the number of cycles spent executing performance-sensitive flags-merging uops. For example, shift CL (merge_arith_flags). For more details, See the Intel? 64 and IA-32 Architectures Optimization Reference Manual.
This event counts the number of cycles with at least one slow LEA uop being allocated. A uop is generally considered as slow LEA if it has three sources (for example, two sources and immediate) regardless of whether it is a result of LEA instruction or not. Examples of the slow LEA uop are or uops with base, index, and offset source operands using base and index reqisters, where base is EBR/RBP/R13, using RIP relative or 16-bit addressing modes. See the Intel? 64 and IA-32 Architectures Optimization Reference Manual for more details about slow LEA instructions.
Resource stalls due to memory buffers or Reservation Station (RS) being fully utilized
Cycles stalled due to no store buffers available. (not including draining form sync).
Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.
number of AVX-256 Computational FP double precision uops issued this cycle
number of GSSE-256 Computational FP single precision uops issued this cycle
Counts cycles weighted by the number of requests waiting for data returning from the memory controller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic units, or LLC.
Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.
Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.
Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.
Counts the number of allocated write entries, include full, partial, and LLC evictions.
Filter on any IRQ or IPQ initiated requests including uncacheable, non-coherent requests.
Filter on cross-core snoops initiated by this Cbox due to LLC eviction.
Filter on cross-core snoops initiated by this Cbox due to external snoop request.
Filter on cross-core snoops initiated by this Cbox due to processor core memory request.
Cycles at least 1 micro-op is executed from any thread on physical core
Cycles at least 2 micro-op is executed from any thread on physical core
Cycles at least 3 micro-op is executed from any thread on physical core
Cycles at least 4 micro-op is executed from any thread on physical core
This event counts the number of Uops issued by the front-end of the pipeilne to the back-end.
Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads
Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread
This event counts the number of retirement slots used each cycle. There are potentially 4 slots that can be used each cycle - meaning, 4 micro-ops or 4 instructions could retire each cycle. This event is used in determining the 'Retiring' category of the Top-Down pipeline slots characterization.
This event counts the number of retirement slots used each cycle. There are potentially 4 slots that can be used each cycle - meaning, 4 micro-ops or 4 instructions could retire each cycle. This event is used in determining the 'Retiring' category of the Top-Down pipeline slots characterization. (Precise Event - PEBS)